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authorMichal Simek <monstr@monstr.eu>2007-03-11 13:48:24 +0100
committerMichal Simek <monstr@monstr.eu>2007-03-11 13:48:24 +0100
commitcfc67116a706fd18b8f6a9c11a16753c5626d689 (patch)
treea8ece1d13504912339bd59cbbc5d29c74c1def4d /cpu/microblaze/start.S
parent76316a318de91f6184e7c22a10e02d275ade2441 (diff)
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[Microblaze][PATCH] part 2
timer support interrupt controller support flash support ethernet support cache support board information support env support booting image support adding support for Xilinx ML401
Diffstat (limited to 'cpu/microblaze/start.S')
-rw-r--r--cpu/microblaze/start.S62
1 files changed, 58 insertions, 4 deletions
diff --git a/cpu/microblaze/start.S b/cpu/microblaze/start.S
index 7efdbb0..bce3297 100644
--- a/cpu/microblaze/start.S
+++ b/cpu/microblaze/start.S
@@ -1,6 +1,8 @@
/*
+ * (C) Copyright 2007 Michal Simek
* (C) Copyright 2004 Atmark Techno, Inc.
*
+ * Michal SIMEK <monstr@monstr.eu>
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
@@ -13,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@@ -27,10 +29,62 @@
.text
.global _start
_start:
+ mts rmsr, r0 /* disable cache */
+ addi r1, r0, CFG_INIT_SP_OFFSET
+ /* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
+ addi r6, r0, 0xb000 /* hex b000 opcode imm */
+ bslli r6, r6, 16 /* shift */
+ swi r6, r0, 0x0 /* reset address */
+ swi r6, r0, 0x8 /* user vector exception */
+ swi r6, r0, 0x10 /* interrupt */
+ swi r6, r0, 0x20 /* hardware exception */
- addi r1, r0, CFG_SDRAM_BASE /* init stack pointer */
- addi r1, r1, CFG_SDRAM_SIZE /* set sp to high up */
+ addi r6, r0, 0xb808 /* hew b808 opcode brai*/
+ bslli r6, r6, 16
+ swi r6, r0, 0x4 /* reset address */
+ swi r6, r0, 0xC /* user vector exception */
+ swi r6, r0, 0x14 /* interrupt */
+ swi r6, r0, 0x24 /* hardware exception */
- brai board_init
+#ifdef CFG_RESET_ADDRESS
+ /* reset address */
+ addik r6, r0, CFG_RESET_ADDRESS
+ sw r6, r1, r0
+ lhu r7, r1, r0
+ shi r7, r0, 0x2
+ shi r6, r0, 0x6
+#endif
+
+#ifdef CFG_USR_EXCEP
+ /* user_vector_exception */
+ addik r6, r0, _exception_handler
+ sw r6, r1, r0
+ lhu r7, r1, r0
+ shi r7, r0, 0xa
+ shi r6, r0, 0xe
+#endif
+
+#ifdef CFG_INTC_0
+ /* interrupt_handler */
+ addik r6, r0, _interrupt_handler
+ sw r6, r1, r0
+ lhu r7, r1, r0
+ shi r7, r0, 0x12
+ shi r6, r0, 0x16
+#endif
+ /* hardware exception */
+ addik r6, r0, _hw_exception_handler
+ sw r6, r1, r0
+ lhu r7, r1, r0
+ shi r7, r0, 0x22
+ shi r6, r0, 0x26
+
+ /* enable instruction and data cache */
+ mfs r12, rmsr
+ ori r12, r12, 0xa0
+ mts rmsr, r12
+
+ /* jumping to board_init */
+ brai board_init
1: bri 1b