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| author | Peter Pearse <peter.pearse@arm.com> | 2007-04-19 13:17:20 +0100 |
|---|---|---|
| committer | Peter Pearse <peter.pearse@arm.com> | 2007-04-19 13:17:20 +0100 |
| commit | ee89bf2782406b1f87088b4764aeb6f811d82526 (patch) | |
| tree | b144476f4b5e92a414efff165d214d34062d4365 /cpu/microblaze/dcache.S | |
| parent | 9c00dfb0bf89c8c23e8af5b5bdf49cf66d769f85 (diff) | |
| parent | 37837828d89084879bee2f2b8c7c68d4695940df (diff) | |
| download | u-boot-imx-ee89bf2782406b1f87088b4764aeb6f811d82526.zip u-boot-imx-ee89bf2782406b1f87088b4764aeb6f811d82526.tar.gz u-boot-imx-ee89bf2782406b1f87088b4764aeb6f811d82526.tar.bz2 | |
Merge with git://www.denx.de/git/u-boot.git
Diffstat (limited to 'cpu/microblaze/dcache.S')
| -rw-r--r-- | cpu/microblaze/dcache.S | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/cpu/microblaze/dcache.S b/cpu/microblaze/dcache.S new file mode 100644 index 0000000..eaf9671 --- /dev/null +++ b/cpu/microblaze/dcache.S @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2007 Michal Simek + * + * Michal SIMEK <monstr@monstr.eu> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + .text + .globl dcache_enable + .ent dcache_enable + .align 2 +dcache_enable: + /* Make space on stack for a temporary */ + addi r1, r1, -4 + /* Save register r12 */ + swi r12, r1, 0 + /* Read the MSR register */ + mfs r12, rmsr + /* Set the instruction enable bit */ + ori r12, r12, 0x80 + /* Save the MSR register */ + mts rmsr, r12 + /* Load register r12 */ + lwi r12, r1, 0 + /* Return */ + rtsd r15, 8 + /* Update stack in the delay slot */ + addi r1, r1, 4 + .end dcache_enable + + .text + .globl dcache_disable + .ent dcache_disable + .align 2 +dcache_disable: + /* Make space on stack for a temporary */ + addi r1, r1, -4 + /* Save register r12 */ + swi r12, r1, 0 + /* Read the MSR register */ + mfs r12, rmsr + /* Clear the data cache enable bit */ + andi r12, r12, ~0x80 + /* Save the MSR register */ + mts rmsr, r12 + /* Load register r12 */ + lwi r12, r1, 0 + /* Return */ + rtsd r15, 8 + /* Update stack in the delay slot */ + addi r1, r1, 4 + .end dcache_disable |