rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

7 files changed, 77 insertions, 77 deletions

diff --git a/cpu/mcf547x_8x/cpu.c b/cpu/mcf547x_8x/cpu.c
index ab4ad28..f9a3544 100644
--- a/cpu/mcf547x_8x/cpu.c
+++ b/cpu/mcf547x_8x/cpu.c
@@ -133,7 +133,7 @@ int watchdog_init(void)
 	volatile gptmr_t *gptmr = (gptmr_t *) (MMAP_GPTMR);
 
 	gptmr->pre = CONFIG_WATCHDOG_TIMEOUT;
-	gptmr->cnt = CFG_TIMER_PRESCALER * 1000;
+	gptmr->cnt = CONFIG_SYS_TIMER_PRESCALER * 1000;
 
 	gptmr->mode = GPT_TMS_SGPIO;
 	gptmr->ctrl = GPT_CTRL_CE | GPT_CTRL_WDEN;
diff --git a/cpu/mcf547x_8x/cpu_init.c b/cpu/mcf547x_8x/cpu_init.c
index 11154c6..9a0e040 100644
--- a/cpu/mcf547x_8x/cpu_init.c
+++ b/cpu/mcf547x_8x/cpu_init.c
@@ -52,40 +52,40 @@ void cpu_init_f(void)
 	xlbarb->pri = 0;
 	xlbarb->prien = 0xff;
 
-#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
-	fbcs->csar0 = CFG_CS0_BASE;
-	fbcs->cscr0 = CFG_CS0_CTRL;
-	fbcs->csmr0 = CFG_CS0_MASK;
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
 #endif
 
-#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
-	fbcs->csar1 = CFG_CS1_BASE;
-	fbcs->cscr1 = CFG_CS1_CTRL;
-	fbcs->csmr1 = CFG_CS1_MASK;
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
+	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
 #endif
 
-#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
-	fbcs->csar2 = CFG_CS2_BASE;
-	fbcs->cscr2 = CFG_CS2_CTRL;
-	fbcs->csmr2 = CFG_CS2_MASK;
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
 #endif
 
-#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
-	fbcs->csar3 = CFG_CS3_BASE;
-	fbcs->cscr3 = CFG_CS3_CTRL;
-	fbcs->csmr3 = CFG_CS3_MASK;
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
 #endif
 
-#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
-	fbcs->csar4 = CFG_CS4_BASE;
-	fbcs->cscr4 = CFG_CS4_CTRL;
-	fbcs->csmr4 = CFG_CS4_MASK;
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
 #endif
 
-#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
-	fbcs->csar5 = CFG_CS5_BASE;
-	fbcs->cscr5 = CFG_CS5_CTRL;
-	fbcs->csmr5 = CFG_CS5_MASK;
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
 #endif
 
 #ifdef CONFIG_FSL_I2C
@@ -110,10 +110,10 @@ int cpu_init_r(void)
 void uart_port_conf(void)
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
-	volatile u8 *pscsicr = (u8 *) (CFG_UART_BASE + 0x40);
+	volatile u8 *pscsicr = (u8 *) (CONFIG_SYS_UART_BASE + 0x40);
 
 	/* Setup Ports: */
-	switch (CFG_UART_PORT) {
+	switch (CONFIG_SYS_UART_PORT) {
 	case 0:
 		gpio->par_psc0 = (GPIO_PAR_PSC0_TXD0 | GPIO_PAR_PSC0_RXD0);
 		break;
diff --git a/cpu/mcf547x_8x/interrupts.c b/cpu/mcf547x_8x/interrupts.c
index d684ffe..76be876 100644
--- a/cpu/mcf547x_8x/interrupts.c
+++ b/cpu/mcf547x_8x/interrupts.c
@@ -28,7 +28,7 @@
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 	intp->imrh0 |= 0xFFFFFFFF;
@@ -42,9 +42,9 @@ int interrupt_init(void)
 #if defined(CONFIG_SLTTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
-	intp->imrh0 &= ~CFG_TMRINTR_MASK;
+	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
+	intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
 }
 #endif
diff --git a/cpu/mcf547x_8x/pci.c b/cpu/mcf547x_8x/pci.c
index 70378b0..f5c2536 100644
--- a/cpu/mcf547x_8x/pci.c
+++ b/cpu/mcf547x_8x/pci.c
@@ -31,9 +31,9 @@
 
 #if defined(CONFIG_PCI)
 /* System RAM mapped over PCI */
-#define CFG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CFG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
-#define CFG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+#define CONFIG_SYS_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
 
 #define cfg_read(val, addr, type, op)		*val = op((type)(addr));
 #define cfg_write(val, addr, type, op)		op((type *)(addr), (val));
@@ -107,9 +107,9 @@ void pci_mcf547x_8x_init(struct pci_controller *hose)
 	pci->tcr1 = PCI_TCR1_P;
 
 	/* Initiator windows */
-	pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
-	pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
-	pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
+	pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
+	pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
+	pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
 
 	pci->iwcr =
 	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
@@ -124,13 +124,13 @@ void pci_mcf547x_8x_init(struct pci_controller *hose)
 	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
 	pci->cr2 = 0;
 
-#ifdef CFG_PCI_BAR0
-	pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
-	pci->tbatr0a = CFG_PCI_TBATR0 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR0
+	pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
+	pci->tbatr0a = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
 #endif
-#ifdef CFG_PCI_BAR1
-	pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
-	pci->tbatr1a = CFG_PCI_TBATR1 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR1
+	pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
+	pci->tbatr1a = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
 #endif
 
 	/* Deassert reset bit */
@@ -141,20 +141,20 @@ void pci_mcf547x_8x_init(struct pci_controller *hose)
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
 
-	pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
-		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
+	pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
 
-	pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
-		       CFG_PCI_IO_SIZE, PCI_REGION_IO);
+	pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
+		       CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
 
-	pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
-		       CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
+	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
+		       CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
 		       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 	hose->region_count = 3;
 
 	hose->cfg_addr = &(pci->car);
-	hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
+	hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
 
 	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
 		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
diff --git a/cpu/mcf547x_8x/slicetimer.c b/cpu/mcf547x_8x/slicetimer.c
index 494f98f..67e8189 100644
--- a/cpu/mcf547x_8x/slicetimer.c
+++ b/cpu/mcf547x_8x/slicetimer.c
@@ -31,22 +31,22 @@ DECLARE_GLOBAL_DATA_PTR;
 static ulong timestamp;
 
 #if defined(CONFIG_SLTTMR)
-#ifndef CFG_UDELAY_BASE
+#ifndef CONFIG_SYS_UDELAY_BASE
 #	error	"uDelay base not defined!"
 #endif
 
-#if !defined(CFG_TMR_BASE) || !defined(CFG_INTR_BASE) || !defined(CFG_TMRINTR_NO) || !defined(CFG_TMRINTR_MASK)
+#if !defined(CONFIG_SYS_TMR_BASE) || !defined(CONFIG_SYS_INTR_BASE) || !defined(CONFIG_SYS_TMRINTR_NO) || !defined(CONFIG_SYS_TMRINTR_MASK)
 #	error	"TMR_BASE, INTR_BASE, TMRINTR_NO or TMRINTR_MASk not defined!"
 #endif
 extern void dtimer_intr_setup(void);
 
 void udelay(unsigned long usec)
 {
-	volatile slt_t *timerp = (slt_t *) (CFG_UDELAY_BASE);
+	volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_UDELAY_BASE);
 	u32 now, freq;
 
 	/* 1 us period */
-	freq = CFG_TIMER_PRESCALER;
+	freq = CONFIG_SYS_TIMER_PRESCALER;
 
 	timerp->cr = 0;		/* Disable */
 	timerp->tcnt = usec * freq;
@@ -62,10 +62,10 @@ void udelay(unsigned long usec)
 
 void dtimer_interrupt(void *not_used)
 {
-	volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE);
+	volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
 
 	/* check for timer interrupt asserted */
-	if ((CFG_TMRPND_REG & CFG_TMRINTR_MASK) == CFG_TMRINTR_PEND) {
+	if ((CONFIG_SYS_TMRPND_REG & CONFIG_SYS_TMRINTR_MASK) == CONFIG_SYS_TMRINTR_PEND) {
 		timerp->sr |= SLT_SR_ST;
 		timestamp++;
 		return;
@@ -74,7 +74,7 @@ void dtimer_interrupt(void *not_used)
 
 void timer_init(void)
 {
-	volatile slt_t *timerp = (slt_t *) (CFG_TMR_BASE);
+	volatile slt_t *timerp = (slt_t *) (CONFIG_SYS_TMR_BASE);
 
 	timestamp = 0;
 
@@ -83,10 +83,10 @@ void timer_init(void)
 	timerp->sr = SLT_SR_BE | SLT_SR_ST;	/* clear status */
 
 	/* initialize and enable timer interrupt */
-	irq_install_handler(CFG_TMRINTR_NO, dtimer_interrupt, 0);
+	irq_install_handler(CONFIG_SYS_TMRINTR_NO, dtimer_interrupt, 0);
 
 	/* Interrupt every ms */
-	timerp->tcnt = 1000 * CFG_TIMER_PRESCALER;
+	timerp->tcnt = 1000 * CONFIG_SYS_TIMER_PRESCALER;
 
 	dtimer_intr_setup();
 
diff --git a/cpu/mcf547x_8x/speed.c b/cpu/mcf547x_8x/speed.c
index 28fe657..2cee488 100644
--- a/cpu/mcf547x_8x/speed.c
+++ b/cpu/mcf547x_8x/speed.c
@@ -37,7 +37,7 @@ int get_clocks(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bus_clk = CFG_CLK;
+	gd->bus_clk = CONFIG_SYS_CLK;
 	gd->cpu_clk = (gd->bus_clk * 2);
 
 #ifdef CONFIG_FSL_I2C
diff --git a/cpu/mcf547x_8x/start.S b/cpu/mcf547x_8x/start.S
index 87355f9..41fc694 100644
--- a/cpu/mcf547x_8x/start.S
+++ b/cpu/mcf547x_8x/start.S
@@ -29,9 +29,9 @@
 #endif
 
 /* last three long word reserved for cache status */
-#define ICACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
-#define DCACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
-#define CACR_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
+#define ICACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
+#define DCACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
+#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
 
 #define _START	_start
 #define _FAULT	_fault
@@ -132,16 +132,16 @@ _start:
 	move.w #0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
-	move.l	#CFG_FLASH_BASE, %d0
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
-	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR0
 
-	move.l	#(CFG_INIT_RAM1_ADDR + CFG_INIT_RAM1_CTRL), %d0
+	move.l	#(CONFIG_SYS_INIT_RAM1_ADDR + CONFIG_SYS_INIT_RAM1_CTRL), %d0
 	movec	%d0, %RAMBAR1
 
-	move.l	#CFG_MBAR, %d0		/* set MBAR address */
+	move.l	#CONFIG_SYS_MBAR, %d0		/* set MBAR address */
 	move.c	%d0, %MBAR
 
 	/* invalidate and disable cache */
@@ -164,7 +164,7 @@ _start:
 
 	/* set stackpointer to end of internal ram to get some stackspace for the
 	   first c-code */
-	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
@@ -195,7 +195,7 @@ relocate_code:
 	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
 	move.l 16(%a6), %a0		/* Save copy of Destination Address */
 
-	move.l #CFG_MONITOR_BASE, %a1
+	move.l #CONFIG_SYS_MONITOR_BASE, %a1
 	move.l #__init_end, %a2
 	move.l %a0, %a3
 
@@ -210,7 +210,7 @@ relocate_code:
  * initialization, now running from RAM.
  */
 	move.l	%a0, %a1
-	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
 	jmp	(%a1)
 
 in_ram:
@@ -220,9 +220,9 @@ clear_bss:
 	 * Now clear BSS segment
 	 */
 	move.l	%a0, %a1
-	add.l	#(_sbss - CFG_MONITOR_BASE),%a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
 	move.l	%a0, %d1
-	add.l	#(_ebss - CFG_MONITOR_BASE),%d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
 6:
 	clr.l	(%a1)+
 	cmp.l	%a1,%d1
@@ -232,11 +232,11 @@ clear_bss:
 	 * fix got table in RAM
 	 */
 	move.l	%a0, %a1
-	add.l	#(__got_start - CFG_MONITOR_BASE),%a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
 	move.l	%a1,%a5		/* * fix got pointer register a5 */
 
 	move.l	%a0, %a2
-	add.l	#(__got_end - CFG_MONITOR_BASE),%a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
 
 7:
 	move.l	(%a1),%d1
@@ -248,7 +248,7 @@ clear_bss:
 
 	/* calculate relative jump to board_init_r in ram */
 	move.l %a0, %a1
-	add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 
 	/* set parameters for board_init_r */
 	move.l %a0,-(%sp)		/* dest_addr */
@@ -281,7 +281,7 @@ _int_handler:
 /* cache functions */
 	.globl	icache_enable
 icache_enable:
-	move.l	#(CFG_SDRAM_BASE + 0x1c000), %d0
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
 	movec	%d0, %ACR2			/* Enable cache */
 
 	move.l	#0x020C8100, %d0		/* Setup cache mask */
@@ -322,7 +322,7 @@ icache_status:
 dcache_enable:
 	bsr	icache_disable
 
-	move.l	#(CFG_SDRAM_BASE + 0xc000), %d0
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0xc000), %d0
 	movec	%d0, %ACR0			/* Enable cache */
 
 	move.l	#0xA30C8100, %d0		/* Invalidate cache cmd */