rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

6 files changed, 126 insertions, 126 deletions

diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c
index 51a9e90..50b4561 100644
--- a/cpu/mcf5445x/cpu_init.c
+++ b/cpu/mcf5445x/cpu_init.c
@@ -62,42 +62,42 @@ void cpu_init_f(void)
 	    GPIO_PAR_FBCTL_TS_TS;
 
 #if !defined(CONFIG_CF_SBF)
-#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
-	fbcs->csar0 = CFG_CS0_BASE;
-	fbcs->cscr0 = CFG_CS0_CTRL;
-	fbcs->csmr0 = CFG_CS0_MASK;
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
+	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
 #endif
 #endif
 
-#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
 	/* Latch chipselect */
-	fbcs->csar1 = CFG_CS1_BASE;
-	fbcs->cscr1 = CFG_CS1_CTRL;
-	fbcs->csmr1 = CFG_CS1_MASK;
+	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
 #endif
 
-#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
-	fbcs->csar2 = CFG_CS2_BASE;
-	fbcs->cscr2 = CFG_CS2_CTRL;
-	fbcs->csmr2 = CFG_CS2_MASK;
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
+	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
 #endif
 
-#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
-	fbcs->csar3 = CFG_CS3_BASE;
-	fbcs->cscr3 = CFG_CS3_CTRL;
-	fbcs->csmr3 = CFG_CS3_MASK;
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
+	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
 #endif
 
-#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
-	fbcs->csar4 = CFG_CS4_BASE;
-	fbcs->cscr4 = CFG_CS4_CTRL;
-	fbcs->csmr4 = CFG_CS4_MASK;
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
+	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
 #endif
 
-#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
-	fbcs->csar5 = CFG_CS5_BASE;
-	fbcs->cscr5 = CFG_CS5_CTRL;
-	fbcs->csmr5 = CFG_CS5_MASK;
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
+	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
 #endif
 
 #ifdef CONFIG_FSL_I2C
@@ -113,11 +113,11 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFRTC
-	volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
+	volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
 	volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
 
-	rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
-	rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
+	rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
+	rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
 #endif
 
 	return (0);
@@ -128,7 +128,7 @@ void uart_port_conf(void)
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CFG_UART_PORT) {
+	switch (CONFIG_SYS_UART_PORT) {
 	case 0:
 		gpio->par_uart =
 		    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
diff --git a/cpu/mcf5445x/dspi.c b/cpu/mcf5445x/dspi.c
index 959d6bd..6d3ebab 100644
--- a/cpu/mcf5445x/dspi.c
+++ b/cpu/mcf5445x/dspi.c
@@ -47,29 +47,29 @@ void dspi_init(void)
 	    DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
 	    DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
 
-#ifdef CFG_DSPI_DCTAR0
-	dspi->dctar0 = CFG_DSPI_DCTAR0;
+#ifdef CONFIG_SYS_DSPI_DCTAR0
+	dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
 #endif
-#ifdef CFG_DSPI_DCTAR1
-	dspi->dctar1 = CFG_DSPI_DCTAR1;
+#ifdef CONFIG_SYS_DSPI_DCTAR1
+	dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
 #endif
-#ifdef CFG_DSPI_DCTAR2
-	dspi->dctar2 = CFG_DSPI_DCTAR2;
+#ifdef CONFIG_SYS_DSPI_DCTAR2
+	dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
 #endif
-#ifdef CFG_DSPI_DCTAR3
-	dspi->dctar3 = CFG_DSPI_DCTAR3;
+#ifdef CONFIG_SYS_DSPI_DCTAR3
+	dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
 #endif
-#ifdef CFG_DSPI_DCTAR4
-	dspi->dctar4 = CFG_DSPI_DCTAR4;
+#ifdef CONFIG_SYS_DSPI_DCTAR4
+	dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
 #endif
-#ifdef CFG_DSPI_DCTAR5
-	dspi->dctar5 = CFG_DSPI_DCTAR5;
+#ifdef CONFIG_SYS_DSPI_DCTAR5
+	dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
 #endif
-#ifdef CFG_DSPI_DCTAR6
-	dspi->dctar6 = CFG_DSPI_DCTAR6;
+#ifdef CONFIG_SYS_DSPI_DCTAR6
+	dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
 #endif
-#ifdef CFG_DSPI_DCTAR7
-	dspi->dctar7 = CFG_DSPI_DCTAR7;
+#ifdef CONFIG_SYS_DSPI_DCTAR7
+	dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
 #endif
 }
 
diff --git a/cpu/mcf5445x/interrupts.c b/cpu/mcf5445x/interrupts.c
index 9572a7b..85828a6 100644
--- a/cpu/mcf5445x/interrupts.c
+++ b/cpu/mcf5445x/interrupts.c
@@ -31,7 +31,7 @@
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 	intp->imrh0 |= 0xFFFFFFFF;
@@ -44,9 +44,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
-	intp->imrh0 &= ~CFG_TMRINTR_MASK;
+	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
+	intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
 }
 #endif
diff --git a/cpu/mcf5445x/pci.c b/cpu/mcf5445x/pci.c
index 0398469..c4a3b05 100644
--- a/cpu/mcf5445x/pci.c
+++ b/cpu/mcf5445x/pci.c
@@ -31,9 +31,9 @@
 
 #if defined(CONFIG_PCI)
 /* System RAM mapped over PCI */
-#define CFG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CFG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
-#define CFG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
+#define CONFIG_SYS_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
 
 #define cfg_read(val, addr, type, op)		*val = op((type)(addr));
 #define cfg_write(val, addr, type, op)		op((type *)(addr), (val));
@@ -80,9 +80,9 @@ void pci_mcf5445x_init(struct pci_controller *hose)
 	pci->tcr1 |= PCI_TCR1_P;
 
 	/* Initiator windows */
-	pci->iw0btar = CFG_PCI_MEM_PHYS | (CFG_PCI_MEM_PHYS >> 16);
-	pci->iw1btar = CFG_PCI_IO_PHYS | (CFG_PCI_IO_PHYS >> 16);
-	pci->iw2btar = CFG_PCI_CFG_PHYS | (CFG_PCI_CFG_PHYS >> 16);
+	pci->iw0btar = CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16);
+	pci->iw1btar = CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16);
+	pci->iw2btar = CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16);
 
 	pci->iwcr =
 	    PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
@@ -97,34 +97,34 @@ void pci_mcf5445x_init(struct pci_controller *hose)
 	pci->cr1 = PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8);
 	pci->cr2 = 0;
 
-#ifdef CFG_PCI_BAR0
-	pci->bar0 = PCI_BAR_BAR0(CFG_PCI_BAR0);
-	pci->tbatr0 = CFG_PCI_TBATR0 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR0
+	pci->bar0 = PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0);
+	pci->tbatr0 = CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN;
 	barEn |= PCI_TCR2_B0E;
 #endif
-#ifdef CFG_PCI_BAR1
-	pci->bar1 = PCI_BAR_BAR1(CFG_PCI_BAR1);
-	pci->tbatr1 = CFG_PCI_TBATR1 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR1
+	pci->bar1 = PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1);
+	pci->tbatr1 = CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN;
 	barEn |= PCI_TCR2_B1E;
 #endif
-#ifdef CFG_PCI_BAR2
-	pci->bar2 = PCI_BAR_BAR2(CFG_PCI_BAR2);
-	pci->tbatr2 = CFG_PCI_TBATR2 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR2
+	pci->bar2 = PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2);
+	pci->tbatr2 = CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN;
 	barEn |= PCI_TCR2_B2E;
 #endif
-#ifdef CFG_PCI_BAR3
-	pci->bar3 = PCI_BAR_BAR3(CFG_PCI_BAR3);
-	pci->tbatr3 = CFG_PCI_TBATR3 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR3
+	pci->bar3 = PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3);
+	pci->tbatr3 = CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN;
 	barEn |= PCI_TCR2_B3E;
 #endif
-#ifdef CFG_PCI_BAR4
-	pci->bar4 = PCI_BAR_BAR4(CFG_PCI_BAR4);
-	pci->tbatr4 = CFG_PCI_TBATR4 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR4
+	pci->bar4 = PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4);
+	pci->tbatr4 = CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN;
 	barEn |= PCI_TCR2_B4E;
 #endif
-#ifdef CFG_PCI_BAR5
-	pci->bar5 = PCI_BAR_BAR5(CFG_PCI_BAR5);
-	pci->tbatr5 = CFG_PCI_TBATR5 | PCI_TBATR_EN;
+#ifdef CONFIG_SYS_PCI_BAR5
+	pci->bar5 = PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5);
+	pci->tbatr5 = CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN;
 	barEn |= PCI_TCR2_B5E;
 #endif
 
@@ -138,20 +138,20 @@ void pci_mcf5445x_init(struct pci_controller *hose)
 	hose->first_busno = 0;
 	hose->last_busno = 0xff;
 
-	pci_set_region(hose->regions + 0, CFG_PCI_MEM_BUS, CFG_PCI_MEM_PHYS,
-		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM);
+	pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
 
-	pci_set_region(hose->regions + 1, CFG_PCI_IO_BUS, CFG_PCI_IO_PHYS,
-		       CFG_PCI_IO_SIZE, PCI_REGION_IO);
+	pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
+		       CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
 
-	pci_set_region(hose->regions + 2, CFG_PCI_SYS_MEM_BUS,
-		       CFG_PCI_SYS_MEM_PHYS, CFG_PCI_SYS_MEM_SIZE,
+	pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
+		       CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
 		       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 	hose->region_count = 3;
 
 	hose->cfg_addr = &(pci->car);
-	hose->cfg_data = (volatile unsigned char *)CFG_PCI_CFG_BUS;
+	hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
 
 	pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
 		    pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
diff --git a/cpu/mcf5445x/speed.c b/cpu/mcf5445x/speed.c
index 6711a1d..9c0c077 100644
--- a/cpu/mcf5445x/speed.c
+++ b/cpu/mcf5445x/speed.c
@@ -94,7 +94,7 @@ int get_clocks(void)
 	u16 fbpll_mask;
 
 #ifdef CONFIG_M54455EVB
-	volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
+	volatile u8 *cpld = (volatile u8 *)(CONFIG_SYS_CS2_BASE + 3);
 #endif
 	u8 bootmode;
 
@@ -145,7 +145,7 @@ int get_clocks(void)
 
 	if (bootmode == 0) {
 		/* RCON mode */
-		vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
+		vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC;
 
 		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
 			/* invaild range, re-set in PCR */
@@ -154,7 +154,7 @@ int get_clocks(void)
 
 			j = (pll->pcr & 0xFF000000) >> 24;
 			for (i = j; i < 0xFF; i++) {
-				vco = i * CFG_INPUT_CLKSRC;
+				vco = i * CONFIG_SYS_INPUT_CLKSRC;
 				if (vco >= CLOCK_PLL_FVCO_MIN) {
 					bus = vco / temp;
 					if (bus <= CLOCK_PLL_FSYS_MIN - MHZ)
@@ -172,25 +172,25 @@ int get_clocks(void)
 		gd->vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 2) {
 		/* Normal mode */
-		vco =  ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
+		vco =  ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
 			/* Default value */
 			pcrvalue = (pll->pcr & 0x00FFFFFF);
 			pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24;
 			pll->pcr = pcrvalue;
-			vco =  ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
+			vco =  ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		}
 		gd->vco_clk = vco;	/* Vco clock */
 	} else if (bootmode == 3) {
 		/* serial mode */
-		vco =  ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
+		vco =  ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
 		gd->vco_clk = vco;	/* Vco clock */
 	}
 
 	if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
 		/* Limp mode */
 	} else {
-		gd->inp_clk = CFG_INPUT_CLKSRC;	/* Input clock */
+		gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
 
 		temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
 		gd->cpu_clk = vco / temp;	/* cpu clock */
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S
index 2a6019b..61e43ff 100644
--- a/cpu/mcf5445x/start.S
+++ b/cpu/mcf5445x/start.S
@@ -29,9 +29,9 @@
 #endif
 
 /* last three long word reserved for cache status */
-#define CACR_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
-#define ICACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
-#define DCACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
+#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
+#define ICACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
+#define DCACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
 
 #define _START	_start
 #define _FAULT	_fault
@@ -47,8 +47,8 @@
 	rte;
 
 #if defined(CONFIG_CF_SBF)
-#define ASM_DRAMINIT	(asm_dram_init - TEXT_BASE + CFG_INIT_RAM_ADDR)
-#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - TEXT_BASE + CFG_INIT_RAM_ADDR)
+#define ASM_DRAMINIT	(asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
 #endif
 
 .text
@@ -149,18 +149,18 @@ asm_sbf_img_hdr:
 	.long	TEXT_BASE	/* image to be relocated at */
 
 asm_dram_init:
-	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1	/* init Rambar */
-	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
 
 	/* Must disable global address */
 	move.l	#0xFC008000, %a1
-	move.l	#(CFG_CS0_BASE), (%a1)
+	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
 	move.l	#0xFC008008, %a1
-	move.l	#(CFG_CS0_CTRL), (%a1)
+	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
 	move.l	#0xFC008004, %a1
-	move.l	#(CFG_CS0_MASK), (%a1)
+	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
 
 	/*
 	 * Dram Initialization
@@ -168,7 +168,7 @@ asm_dram_init:
 	 */
 	/* mscr sdram */
 	move.l	#0xFC0A4074, %a1
-	move.b	#(CFG_SDRAM_DRV_STRENGTH), (%a1)
+	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
 	nop
 
 	/* SDRAM Chip 0 and 1 */
@@ -177,8 +177,8 @@ asm_dram_init:
 
 	/* calculate the size */
 	move.l	#0x13, %d1
-	move.l	#(CFG_SDRAM_SIZE), %d2
-#ifdef CFG_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
 	lsr.l	#1, %d2
 #endif
 
@@ -189,20 +189,20 @@ dramsz_loop:
 	bne	dramsz_loop
 
 	/* SDRAM Chip 0 and 1 */
-	move.l	#(CFG_SDRAM_BASE), (%a1)
+	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
 	or.l	%d1, (%a1)
-#ifdef CFG_SDRAM_BASE1
-	move.l	#(CFG_SDRAM_BASE1), (%a2)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
 	or.l	%d1, (%a2)
 #endif
 	nop
 
 	/* dram cfg1 and cfg2 */
 	move.l	#0xFC0B8008, %a1
-	move.l	#(CFG_SDRAM_CFG1), (%a1)
+	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
 	nop
 	move.l	#0xFC0B800C, %a2
-	move.l	#(CFG_SDRAM_CFG2), (%a2)
+	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
 	nop
 
 	move.l	#0xFC0B8000, %a1	/* Mode */
@@ -210,13 +210,13 @@ dramsz_loop:
 
 #ifdef CONFIG_M54455EVB
 	/* Issue PALL */
-	move.l	#(CFG_SDRAM_CTRL + 2), (%a2)
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
 	nop
 
 	/* Issue LEMR */
-	move.l	#(CFG_SDRAM_EMOD + 0x408), (%a1)
+	move.l	#(CONFIG_SYS_SDRAM_EMOD + 0x408), (%a1)
 	nop
-	move.l	#(CFG_SDRAM_MODE + 0x300), (%a1)
+	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x300), (%a1)
 	nop
 
 	move.l	#1000, %d0
@@ -227,24 +227,24 @@ wait1000:
 #endif
 
 	/* Issue PALL */
-	move.l	#(CFG_SDRAM_CTRL + 2), (%a2)
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
 	nop
 
 	/* Perform two refresh cycles */
-	move.l	#(CFG_SDRAM_CTRL + 4), %d0
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
 	nop
 	move.l	%d0, (%a2)
 	move.l	%d0, (%a2)
 	nop
 
 #ifdef CONFIG_M54455EVB
-	move.l	#(CFG_SDRAM_MODE + 0x200), (%a1)
+	move.l	#(CONFIG_SYS_SDRAM_MODE + 0x200), (%a1)
 	nop
 #elif defined(CONFIG_M54451EVB)
 	/* Issue LEMR */
-	move.l	#(CFG_SDRAM_MODE), (%a2)
+	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a2)
 	nop
-	move.l	#(CFG_SDRAM_EMOD), (%a2)
+	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a2)
 	nop
 #endif
 
@@ -254,7 +254,7 @@ wait500:
 	subq.l	#1, %d0
 	bne	wait500
 
-	move.l	#(CFG_SDRAM_CTRL), %d0
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d0
 	and.l	#0x7FFFFFFF, %d0
 #ifdef CONFIG_M54455EVB
 	or.l	#0x10000c00, %d0
@@ -290,8 +290,8 @@ wait500:
 	move.l	(%a1)+, %d5
 	move.l	(%a1), %a4
 
-	move.l	#(CFG_INIT_RAM_ADDR + CFG_SBFHDR_DATA_OFFSET), %a0
-	move.l	#(CFG_SBFHDR_SIZE), %d4
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
+	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
 
 	move.l	#0xFC05C02C, %a1	/* dspi status */
 
@@ -381,10 +381,10 @@ _start:
 	move.l	#TEXT_BASE, %d0
 	movec	%d0, %VBR
 #else
-	move.l	#CFG_FLASH_BASE, %d0
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
-	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
 #endif
 
@@ -408,7 +408,7 @@ _start:
 
 	/* set stackpointer to end of internal ram to get some stackspace for
 	   the first c-code */
-	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
@@ -439,7 +439,7 @@ relocate_code:
 	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
 	move.l 16(%a6), %a0		/* Save copy of Destination Address */
 
-	move.l #CFG_MONITOR_BASE, %a1
+	move.l #CONFIG_SYS_MONITOR_BASE, %a1
 	move.l #__init_end, %a2
 	move.l %a0, %a3
 
@@ -454,7 +454,7 @@ relocate_code:
  * initialization, now running from RAM.
  */
 	move.l	%a0, %a1
-	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
 	jmp	(%a1)
 
 in_ram:
@@ -464,9 +464,9 @@ clear_bss:
 	 * Now clear BSS segment
 	 */
 	move.l	%a0, %a1
-	add.l	#(_sbss - CFG_MONITOR_BASE),%a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
 	move.l	%a0, %d1
-	add.l	#(_ebss - CFG_MONITOR_BASE),%d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
 6:
 	clr.l	(%a1)+
 	cmp.l	%a1,%d1
@@ -476,11 +476,11 @@ clear_bss:
 	 * fix got table in RAM
 	 */
 	move.l	%a0, %a1
-	add.l	#(__got_start - CFG_MONITOR_BASE),%a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
 	move.l	%a1,%a5			/* * fix got pointer register a5 */
 
 	move.l	%a0, %a2
-	add.l	#(__got_end - CFG_MONITOR_BASE),%a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
 
 7:
 	move.l	(%a1),%d1
@@ -492,7 +492,7 @@ clear_bss:
 
 	/* calculate relative jump to board_init_r in ram */
 	move.l %a0, %a1
-	add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 
 	/* set parameters for board_init_r */
 	move.l %a0,-(%sp)		/* dest_addr */
@@ -531,7 +531,7 @@ icache_enable:
 	move.l	#0x00040100, %d0	/* Invalidate icache */
 	movec	%d0, %CACR
 
-	move.l	#(CFG_SDRAM_BASE + 0x1c000), %d0	/* Setup icache */
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0	/* Setup icache */
 	movec	%d0, %ACR2
 
 	move.l	#0x04088020, %d0	/* Enable bcache and icache */