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authorTsiChung Liew <Tsi-Chung.Liew@freescale.com>2008-07-23 20:38:53 -0500
committerJohn Rigby <jrigby@freescale.com>2008-08-14 12:31:55 -0600
commit9f751551456828b2d0ff417f10959fb0c7110bd0 (patch)
tree9400ee01bbef8c6d3dde6249bda85e6fc8405c4f /cpu/mcf5445x/speed.c
parenta7323bba229203aae2604afde131ab47bad4eadc (diff)
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ColdFire: Implement SBF feature for M5445EVB
Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'cpu/mcf5445x/speed.c')
-rw-r--r--cpu/mcf5445x/speed.c67
1 files changed, 47 insertions, 20 deletions
diff --git a/cpu/mcf5445x/speed.c b/cpu/mcf5445x/speed.c
index 967becf..f677f3c 100644
--- a/cpu/mcf5445x/speed.c
+++ b/cpu/mcf5445x/speed.c
@@ -84,26 +84,29 @@ void clock_exit_limp(void)
*/
int get_clocks(void)
{
+
volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
- volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
- volatile u8 *fpga = (volatile u8 *)(CFG_CS3_BASE + 14);
int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
int pllmult_pci[] = { 12, 6, 16, 8 };
- int vco, bPci, temp, fbtemp, pcrvalue;
+ int vco = 0, bPci, temp, fbtemp, pcrvalue;
int *pPllmult = NULL;
u16 fbpll_mask;
- u8 cpldmode;
+
+#ifdef CONFIG_M54455EVB
+ volatile u8 *cpld = (volatile u8 *)(CFG_CS2_BASE + 3);
+#endif
+ u8 bootmode;
/* To determine PCI is present or not */
if (((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x00e0) ||
((ccm->ccr & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
pPllmult = &pllmult_pci[0];
- fbpll_mask = 3;
+ fbpll_mask = 3; /* 11b */
bPci = 1;
} else {
pPllmult = &pllmult_nopci[0];
- fbpll_mask = 7;
+ fbpll_mask = 7; /* 111b */
#ifdef CONFIG_PCI
gd->pci_clk = 0;
#endif
@@ -111,20 +114,36 @@ int get_clocks(void)
}
#ifdef CONFIG_M54455EVB
- /* Temporary place here, belongs in board/freescale/... */
- /* Temporary read from CCR- fixed fb issue, must be the same clock
- as pci or input clock, causing cpld/fpga read inconsistancy */
- fbtemp = pPllmult[ccm->ccr & fbpll_mask];
+ bootmode = (*cpld & 0x03);
- /* Break down into small pieces, code still in flex bus */
- pcrvalue = pll->pcr & 0xFFFFF0FF;
- temp = fbtemp - 1;
- pcrvalue |= PLL_PCR_OUTDIV3(temp);
+ if (bootmode != 3) {
+ /* Temporary read from CCR- fixed fb issue, must be the same clock
+ as pci or input clock, causing cpld/fpga read inconsistancy */
+ fbtemp = pPllmult[ccm->ccr & fbpll_mask];
+ /* Break down into small pieces, code still in flex bus */
+ pcrvalue = pll->pcr & 0xFFFFF0FF;
+ temp = fbtemp - 1;
+ pcrvalue |= PLL_PCR_OUTDIV3(temp);
+
+ pll->pcr = pcrvalue;
+ }
+#endif
+#ifdef CONFIG_M54451EVB
+ /* No external logic to read the bootmode, hard coded from built */
+#ifdef CONFIG_CF_SBF
+ bootmode = 3;
+#else
+ bootmode = 2;
+
+ /* default value is 16 mul, set to 20 mul */
+ pcrvalue = (pll->pcr & 0x00FFFFFF) | 0x14000000;
pll->pcr = pcrvalue;
+ while ((pll->psr & PLL_PSR_LOCK) != PLL_PSR_LOCK);
+#endif
+#endif
- cpldmode = *cpld & 0x03;
- if (cpldmode == 0) {
+ if (bootmode == 0) {
/* RCON mode */
vco = pPllmult[ccm->rcon & fbpll_mask] * CFG_INPUT_CLKSRC;
@@ -151,14 +170,22 @@ int get_clocks(void)
pll->pcr = pcrvalue;
}
gd->vco_clk = vco; /* Vco clock */
- } else if (cpldmode == 2) {
+ } else if (bootmode == 2) {
/* Normal mode */
- vco = pPllmult[ccm->ccr & fbpll_mask] * CFG_INPUT_CLKSRC;
+ vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
+ if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
+ /* Default value */
+ pcrvalue = (pll->pcr & 0x00FFFFFF);
+ pcrvalue |= pPllmult[ccm->ccr & fbpll_mask] << 24;
+ pll->pcr = pcrvalue;
+ vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
+ }
gd->vco_clk = vco; /* Vco clock */
- } else if (cpldmode == 3) {
+ } else if (bootmode == 3) {
/* serial mode */
+ vco = ((pll->pcr & 0xFF000000) >> 24) * CFG_INPUT_CLKSRC;
+ gd->vco_clk = vco; /* Vco clock */
}
-#endif /* CONFIG_M54455EVB */
if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
/* Limp mode */