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| author | TsiChung Liew <tsicliew@gmail.com> | 2009-06-30 14:18:29 +0000 |
|---|---|---|
| committer | TsiChung Liew <Tsi-Chung.Liew@freescale.com> | 2009-07-14 09:46:34 -0500 |
| commit | ee0a8462466dd284968536eb57c6eef4be0d6aad (patch) | |
| tree | c04da824a3026d53f054dd544cc22115c37a1644 /cpu/mcf5445x/cpu_init.c | |
| parent | dec61c7851baa72151ef1d3657e7bb3b68907d48 (diff) | |
| download | u-boot-imx-ee0a8462466dd284968536eb57c6eef4be0d6aad.zip u-boot-imx-ee0a8462466dd284968536eb57c6eef4be0d6aad.tar.gz u-boot-imx-ee0a8462466dd284968536eb57c6eef4be0d6aad.tar.bz2 | |
ColdFire: Add DSPI support for MCF5227x and MCF5445x
Remove individual CPU specific DSPI driver.
Add required feature for the common DSPI driver in cpu_init and
in platform configuration file.
Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
Diffstat (limited to 'cpu/mcf5445x/cpu_init.c')
| -rw-r--r-- | cpu/mcf5445x/cpu_init.c | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/cpu/mcf5445x/cpu_init.c b/cpu/mcf5445x/cpu_init.c index 7e04e32..48b37df 100644 --- a/cpu/mcf5445x/cpu_init.c +++ b/cpu/mcf5445x/cpu_init.c @@ -171,3 +171,69 @@ int fecpin_setclear(struct eth_device *dev, int setclear) return 0; } #endif + +#ifdef CONFIG_CF_DSPI +void cfspi_port_conf(void) +{ + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + gpio->par_dspi = GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT | + GPIO_PAR_DSPI_SCK_SCK; +} + +int cfspi_claim_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS) + return -1; + + /* Clear FIFO and resume transfer */ + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 1: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS1_PCS1; + break; + case 2: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS2_PCS2; + break; + case 5: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; + gpio->par_dspi |= GPIO_PAR_DSPI_PCS5_PCS5; + break; + } + + return 0; +} + +void cfspi_release_bus(uint bus, uint cs) +{ + volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; + + dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */ + + switch (cs) { + case 0: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; + break; + case 1: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS1_PCS1; + break; + case 2: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS2_PCS2; + break; + case 5: + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS5_PCS5; + break; + } +} +#endif |