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| author | Heiko Schocher <hs@pollux.denx.de> | 2006-04-20 08:42:42 +0200 |
|---|---|---|
| committer | Heiko Schocher <hs@pollux.denx.de> | 2006-04-20 08:42:42 +0200 |
| commit | 9acb626fc145e7327f94fd77f927dce08dd978a8 (patch) | |
| tree | 8597a60515c10ec608ad756699460226ccb63343 /cpu/mcf52x2/fec.c | |
| parent | 8419c013048b1f15f3fa2fc7c0463d860a04ee3e (diff) | |
| download | u-boot-imx-9acb626fc145e7327f94fd77f927dce08dd978a8.zip u-boot-imx-9acb626fc145e7327f94fd77f927dce08dd978a8.tar.gz u-boot-imx-9acb626fc145e7327f94fd77f927dce08dd978a8.tar.bz2 | |
Add MCF5282 support (without preloader)
relocate ichache_State to ram
u-boot can run from internal flash
Add EB+MCF-EV123 board support.
Add m68k Boards to MAKEALL
Patch from Jens Scharsig, 08 Aug 2005
Diffstat (limited to 'cpu/mcf52x2/fec.c')
| -rw-r--r-- | cpu/mcf52x2/fec.c | 27 |
1 files changed, 22 insertions, 5 deletions
diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c index a5c50af..b8b82d0 100644 --- a/cpu/mcf52x2/fec.c +++ b/cpu/mcf52x2/fec.c @@ -200,7 +200,9 @@ int eth_rx (void) int eth_init (bd_t * bd) { - +#ifndef CFG_ENET_BD_BASE + DECLARE_GLOBAL_DATA_PTR; +#endif int i; volatile fec_t *fecp = (fec_t *) (FEC_ADDR); @@ -242,9 +244,13 @@ int eth_init (bd_t * bd) /* Clear multicast address hash table */ +#ifdef CONFIG_M5282 + fecp->fec_ihash_table_high = 0; + fecp->fec_ihash_table_low = 0; +#else fecp->fec_hash_table_high = 0; fecp->fec_hash_table_low = 0; - +#endif /* Set maximum receive buffer size. */ fecp->fec_r_buff_size = PKT_MAXBLR_SIZE; @@ -256,7 +262,16 @@ int eth_init (bd_t * bd) txIdx = 0; if (!rtx) { +#ifdef CFG_ENET_BD_BASE rtx = (RTXBD *) CFG_ENET_BD_BASE; +#else + rtx = (RTXBD *) (CFG_MONITOR_BASE+gd->reloc_off - + (((PKTBUFSRX+TX_BUF_CNT)*+sizeof(cbd_t) + +0xFF) + & ~0xFF) + ); + debug("set ENET_DB_BASE to %lX\n",(long) rtx); +#endif } /* @@ -294,11 +309,13 @@ int eth_init (bd_t * bd) fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE; fecp->fec_x_cntrl = FEC_TCNTRL_FDEN; #else /* Half duplex mode */ - fecp->fec_r_cntrl = FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; + fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16); /* set max frame length */ + fecp->fec_r_cntrl |= FEC_RCNTRL_MII_MODE | FEC_RCNTRL_DRT; fecp->fec_x_cntrl = 0; #endif /* Set MII speed */ - fecp->fec_mii_speed = 0x0e; + fecp->fec_mii_speed = (((CFG_CLK / 2) / (2500000 / 10)) + 5) / 10; + fecp->fec_mii_speed *= 2; /* Configure port B for MII. */ @@ -402,7 +419,7 @@ static void mii_discover_phy (void) */ udelay (10000); /* wait 10ms */ } - for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + for (phyno = 1; phyno < 32 && phyaddr < 0; ++phyno) { phytype = mii_send (mk_mii_read (phyno, PHY_PHYIDR1)); #ifdef ET_DEBUG printf ("PHY type 0x%x pass %d type ", phytype, pass); |