summaryrefslogtreecommitdiff
path: root/cpu/mcf52x2/fec.c
diff options
context:
space:
mode:
authorMarian Balakowicz <m8@semihalf.com>2005-10-28 22:30:33 +0200
committerMarian Balakowicz <m8@semihalf.com>2005-10-28 22:30:33 +0200
commit63ff004c4fcad9f690bf44dbd15d568bb47aac2d (patch)
tree7b64074a85da8118b6c862f14de1171b36ade0f7 /cpu/mcf52x2/fec.c
parentfe93483a0ab9dcbf7794ffbf0b029ba138380e81 (diff)
downloadu-boot-imx-63ff004c4fcad9f690bf44dbd15d568bb47aac2d.zip
u-boot-imx-63ff004c4fcad9f690bf44dbd15d568bb47aac2d.tar.gz
u-boot-imx-63ff004c4fcad9f690bf44dbd15d568bb47aac2d.tar.bz2
Add support for multiple PHYs.
Diffstat (limited to 'cpu/mcf52x2/fec.c')
-rw-r--r--cpu/mcf52x2/fec.c18
1 files changed, 15 insertions, 3 deletions
diff --git a/cpu/mcf52x2/fec.c b/cpu/mcf52x2/fec.c
index 623a01d..3bf3c8d 100644
--- a/cpu/mcf52x2/fec.c
+++ b/cpu/mcf52x2/fec.c
@@ -519,7 +519,8 @@ void mii_init (void)
* Otherwise they hang in mii_send() !!! Sorry!
*****************************************************************************/
-int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
+int mcf52x2_miiphy_read (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short *value)
{
short rdreg; /* register working value */
@@ -537,7 +538,8 @@ int miiphy_read (unsigned char addr, unsigned char reg, unsigned short *value)
return 0;
}
-int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
+int mcf52x2_miiphy_write (char *devname, unsigned char addr,
+ unsigned char reg, unsigned short value)
{
short rdreg; /* register working value */
@@ -554,5 +556,15 @@ int miiphy_write (unsigned char addr, unsigned char reg, unsigned short value)
return 0;
}
#endif /* (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII) */
-
#endif /* CFG_CMD_NET, FEC_ENET */
+
+int mcf52x2_miiphy_initialize(bd_t *bis)
+{
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
+#if (CONFIG_COMMANDS & CFG_CMD_MII) && !defined(CONFIG_BITBANGMII)
+ miiphy_register("mcf52x2phy", mcf52x2_miiphy_read, mcf52x2_miiphy_write);
+#endif
+#endif
+ return 0;
+}
+