summaryrefslogtreecommitdiff
path: root/cpu/mcf52x2/cpu_init.c
diff options
context:
space:
mode:
authorTsiChungLiew <Tsi-Chung.Liew@freescale.com>2007-08-15 19:21:21 -0500
committerJohn Rigby <jrigby@freescale.com>2007-08-16 17:43:20 -0600
commit83ec20bc4380eebddfde45da6e3a69a92d4db21d (patch)
tree57cbcef9eb99d47da3812cc43b34a97c9c27edd1 /cpu/mcf52x2/cpu_init.c
parentf52e78304dcc0ac459c0ea1fa5be275c7d1642cf (diff)
downloadu-boot-imx-83ec20bc4380eebddfde45da6e3a69a92d4db21d.zip
u-boot-imx-83ec20bc4380eebddfde45da6e3a69a92d4db21d.tar.gz
u-boot-imx-83ec20bc4380eebddfde45da6e3a69a92d4db21d.tar.bz2
ColdFire: MCF52x2 update
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com>
Diffstat (limited to 'cpu/mcf52x2/cpu_init.c')
-rw-r--r--cpu/mcf52x2/cpu_init.c382
1 files changed, 208 insertions, 174 deletions
diff --git a/cpu/mcf52x2/cpu_init.c b/cpu/mcf52x2/cpu_init.c
index 1748ea9..5736d0f 100644
--- a/cpu/mcf52x2/cpu_init.c
+++ b/cpu/mcf52x2/cpu_init.c
@@ -27,28 +27,10 @@
#include <common.h>
#include <watchdog.h>
-
-#ifdef CONFIG_M5271
-#include <asm/m5271.h>
-#include <asm/immap_5271.h>
-#endif
-
-#ifdef CONFIG_M5272
-#include <asm/m5272.h>
-#include <asm/immap_5272.h>
-#endif
-
-#ifdef CONFIG_M5282
-#include <asm/m5282.h>
-#include <asm/immap_5282.h>
-#endif
-
-#ifdef CONFIG_M5249
-#include <asm/m5249.h>
-#endif
+#include <asm/immap.h>
#if defined(CONFIG_M5271)
-void cpu_init_f (void)
+void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* Disable the watchdog if we aren't using it */
@@ -58,25 +40,35 @@ void cpu_init_f (void)
/* Set clockspeed to 100MHz */
mbar_writeShort(MCF_FMPLL_SYNCR,
MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
- while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK);
-
- /* Enable UART pins */
- mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
- MCF_GPIO_PAR_UART_U0RXD |
- MCF_GPIO_PAR_UART_U1RXD_UART1 |
- MCF_GPIO_PAR_UART_U1TXD_UART1);
-
- /* Enable Ethernet pins */
- mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+ while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
}
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
+ MCF_GPIO_PAR_UART_U0RXD);
+ break;
+ case 1:
+ mbar_writeShort(MCF_GPIO_PAR_UART,
+ MCF_GPIO_PAR_UART_U1RXD_UART1 |
+ MCF_GPIO_PAR_UART_U1TXD_UART1);
+ break;
+ case 2:
+ mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
+ break;
+ }
+}
#endif
#if defined(CONFIG_M5272)
@@ -87,69 +79,68 @@ int cpu_init_r (void)
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (void)
+void cpu_init_f(void)
{
/* if we come from RAM we assume the CPU is
* already initialized.
*/
#ifndef CONFIG_MONITOR_IS_IN_RAM
- volatile immap_t *regp = (immap_t *)CFG_MBAR;
-
- volatile unsigned char *mbar;
- mbar = (volatile unsigned char *) CFG_MBAR;
+ volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
+ volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
+ volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
- regp->sysctrl_reg.sc_scr = CFG_SCR;
- regp->sysctrl_reg.sc_spr = CFG_SPR;
+ sysctrl->sc_scr = CFG_SCR;
+ sysctrl->sc_spr = CFG_SPR;
/* Setup Ports: */
- regp->gpio_reg.gpio_pacnt = CFG_PACNT;
- regp->gpio_reg.gpio_paddr = CFG_PADDR;
- regp->gpio_reg.gpio_padat = CFG_PADAT;
- regp->gpio_reg.gpio_pbcnt = CFG_PBCNT;
- regp->gpio_reg.gpio_pbddr = CFG_PBDDR;
- regp->gpio_reg.gpio_pbdat = CFG_PBDAT;
- regp->gpio_reg.gpio_pdcnt = CFG_PDCNT;
+ gpio->gpio_pacnt = CFG_PACNT;
+ gpio->gpio_paddr = CFG_PADDR;
+ gpio->gpio_padat = CFG_PADAT;
+ gpio->gpio_pbcnt = CFG_PBCNT;
+ gpio->gpio_pbddr = CFG_PBDDR;
+ gpio->gpio_pbdat = CFG_PBDAT;
+ gpio->gpio_pdcnt = CFG_PDCNT;
/* Memory Controller: */
- regp->csctrl_reg.cs_br0 = CFG_BR0_PRELIM;
- regp->csctrl_reg.cs_or0 = CFG_OR0_PRELIM;
+ csctrl->cs_br0 = CFG_BR0_PRELIM;
+ csctrl->cs_or0 = CFG_OR0_PRELIM;
#if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
- regp->csctrl_reg.cs_br1 = CFG_BR1_PRELIM;
- regp->csctrl_reg.cs_or1 = CFG_OR1_PRELIM;
+ csctrl->cs_br1 = CFG_BR1_PRELIM;
+ csctrl->cs_or1 = CFG_OR1_PRELIM;
#endif
#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
- regp->csctrl_reg.cs_br2 = CFG_BR2_PRELIM;
- regp->csctrl_reg.cs_or2 = CFG_OR2_PRELIM;
+ csctrl->cs_br2 = CFG_BR2_PRELIM;
+ csctrl->cs_or2 = CFG_OR2_PRELIM;
#endif
#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
- regp->csctrl_reg.cs_br3 = CFG_BR3_PRELIM;
- regp->csctrl_reg.cs_or3 = CFG_OR3_PRELIM;
+ csctrl->cs_br3 = CFG_BR3_PRELIM;
+ csctrl->cs_or3 = CFG_OR3_PRELIM;
#endif
#if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
- regp->csctrl_reg.cs_br4 = CFG_BR4_PRELIM;
- regp->csctrl_reg.cs_or4 = CFG_OR4_PRELIM;
+ csctrl->cs_br4 = CFG_BR4_PRELIM;
+ csctrl->cs_or4 = CFG_OR4_PRELIM;
#endif
#if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
- regp->csctrl_reg.cs_br5 = CFG_BR5_PRELIM;
- regp->csctrl_reg.cs_or5 = CFG_OR5_PRELIM;
+ csctrl->cs_br5 = CFG_BR5_PRELIM;
+ csctrl->cs_or5 = CFG_OR5_PRELIM;
#endif
#if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
- regp->csctrl_reg.cs_br6 = CFG_BR6_PRELIM;
- regp->csctrl_reg.cs_or6 = CFG_OR6_PRELIM;
+ csctrl->cs_br6 = CFG_BR6_PRELIM;
+ csctrl->cs_or6 = CFG_OR6_PRELIM;
#endif
#if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
- regp->csctrl_reg.cs_br7 = CFG_BR7_PRELIM;
- regp->csctrl_reg.cs_or7 = CFG_OR7_PRELIM;
+ csctrl->cs_br7 = CFG_BR7_PRELIM;
+ csctrl->cs_or7 = CFG_OR7_PRELIM;
#endif
-#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
+#endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
/* enable instruction cache now */
icache_enable();
@@ -159,14 +150,30 @@ void cpu_init_f (void)
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
-#endif /* #if defined(CONFIG_M5272) */
+void uart_port_conf(void)
+{
+ volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
+ gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
+ break;
+ case 1:
+ gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
+ gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5272) */
-#ifdef CONFIG_M5282
+#if defined(CONFIG_M5282)
/*
* Breath some life into the CPU...
*
@@ -174,7 +181,7 @@ int cpu_init_r (void)
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (void)
+void cpu_init_f(void)
{
#ifndef CONFIG_WATCHDOG
/* disable watchdog if we aren't using it */
@@ -183,7 +190,11 @@ void cpu_init_f (void)
#ifndef CONFIG_MONITOR_IS_IN_RAM
/* Set speed /PLL */
- MCFCLOCK_SYNCR = MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
+ MCFCLOCK_SYNCR =
+ MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
+ while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
+
+ MCFGPIO_PBCDPAR = 0xc0;
/* Set up the GPIO ports */
#ifdef CFG_PEPAR
@@ -228,29 +239,28 @@ void cpu_init_f (void)
defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
defined(CFG_CS0_WS)
- MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
-
- #if (CFG_CS0_WIDTH == 8)
- #define CFG_CS0_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS0_WIDTH == 16)
- #define CFG_CS0_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS0_WIDTH == 32)
- #define CFG_CS0_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
- #endif
- MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
- |CFG_CS0_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS0_RO != 0)
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)
- |MCFCSM_CSMR_WP|MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE-1)|MCFCSM_CSMR_V;
- #endif
+ MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
+
+#if (CFG_CS0_WIDTH == 8)
+#define CFG_CS0_PS MCFCSM_CSCR_PS_8
+#elif (CFG_CS0_WIDTH == 16)
+#define CFG_CS0_PS MCFCSM_CSCR_PS_16
+#elif (CFG_CS0_WIDTH == 32)
+#define CFG_CS0_PS MCFCSM_CSCR_PS_32
#else
- #waring "Chip Select 0 are not initialized/used"
+#error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
+#endif
+ MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
+ | CFG_CS0_PS | MCFCSM_CSCR_AA;
+
+#if (CFG_CS0_RO != 0)
+ MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
+ | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
+#else
+ MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
+#endif
+#else
+#waring "Chip Select 0 are not initialized/used"
#endif
#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
@@ -259,29 +269,27 @@ void cpu_init_f (void)
MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
- #if (CFG_CS1_WIDTH == 8)
- #define CFG_CS1_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS1_WIDTH == 16)
- #define CFG_CS1_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS1_WIDTH == 32)
- #define CFG_CS1_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
- #endif
- MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
- |CFG_CS1_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS1_RO != 0)
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
- |MCFCSM_CSMR_WP
- |MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE-1)
- |MCFCSM_CSMR_V;
- #endif
+#if (CFG_CS1_WIDTH == 8)
+#define CFG_CS1_PS MCFCSM_CSCR_PS_8
+#elif (CFG_CS1_WIDTH == 16)
+#define CFG_CS1_PS MCFCSM_CSCR_PS_16
+#elif (CFG_CS1_WIDTH == 32)
+#define CFG_CS1_PS MCFCSM_CSCR_PS_32
+#else
+#error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
+#endif
+ MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
+ | CFG_CS1_PS | MCFCSM_CSCR_AA;
+
+#if (CFG_CS1_RO != 0)
+ MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
+ | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
+#else
+ MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
+ | MCFCSM_CSMR_V;
+#endif
#else
- #warning "Chip Select 1 are not initialized/used"
+#warning "Chip Select 1 are not initialized/used"
#endif
#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
@@ -290,29 +298,27 @@ void cpu_init_f (void)
MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
- #if (CFG_CS2_WIDTH == 8)
- #define CFG_CS2_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS2_WIDTH == 16)
- #define CFG_CS2_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS2_WIDTH == 32)
- #define CFG_CS2_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
- #endif
- MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
- |CFG_CS2_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS2_RO != 0)
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
- |MCFCSM_CSMR_WP
- |MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE-1)
- |MCFCSM_CSMR_V;
- #endif
+#if (CFG_CS2_WIDTH == 8)
+#define CFG_CS2_PS MCFCSM_CSCR_PS_8
+#elif (CFG_CS2_WIDTH == 16)
+#define CFG_CS2_PS MCFCSM_CSCR_PS_16
+#elif (CFG_CS2_WIDTH == 32)
+#define CFG_CS2_PS MCFCSM_CSCR_PS_32
#else
- #warning "Chip Select 2 are not initialized/used"
+#error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
+#endif
+ MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
+ | CFG_CS2_PS | MCFCSM_CSCR_AA;
+
+#if (CFG_CS2_RO != 0)
+ MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
+ | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
+#else
+ MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
+ | MCFCSM_CSMR_V;
+#endif
+#else
+#warning "Chip Select 2 are not initialized/used"
#endif
#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
@@ -321,32 +327,30 @@ void cpu_init_f (void)
MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
- #if (CFG_CS3_WIDTH == 8)
- #define CFG_CS3_PS MCFCSM_CSCR_PS_8
- #elif (CFG_CS3_WIDTH == 16)
- #define CFG_CS3_PS MCFCSM_CSCR_PS_16
- #elif (CFG_CS3_WIDTH == 32)
- #define CFG_CS3_PS MCFCSM_CSCR_PS_32
- #else
- #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
- #endif
- MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
- |CFG_CS3_PS
- |MCFCSM_CSCR_AA;
-
- #if (CFG_CS3_RO != 0)
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
- |MCFCSM_CSMR_WP
- |MCFCSM_CSMR_V;
- #else
- MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE-1)
- |MCFCSM_CSMR_V;
- #endif
+#if (CFG_CS3_WIDTH == 8)
+#define CFG_CS3_PS MCFCSM_CSCR_PS_8
+#elif (CFG_CS3_WIDTH == 16)
+#define CFG_CS3_PS MCFCSM_CSCR_PS_16
+#elif (CFG_CS3_WIDTH == 32)
+#define CFG_CS3_PS MCFCSM_CSCR_PS_32
+#else
+#error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
+#endif
+ MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
+ | CFG_CS3_PS | MCFCSM_CSCR_AA;
+
+#if (CFG_CS3_RO != 0)
+ MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
+ | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
+#else
+ MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
+ | MCFCSM_CSMR_V;
+#endif
#else
- #warning "Chip Select 3 are not initialized/used"
+#warning "Chip Select 3 are not initialized/used"
#endif
-#endif /* CONFIG_MONITOR_IS_IN_RAM */
+#endif /* CONFIG_MONITOR_IS_IN_RAM */
/* defer enabling cache until boot (see do_go) */
/* icache_enable(); */
@@ -355,10 +359,29 @@ void cpu_init_f (void)
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ MCFGPIO_PUAPAR &= 0xFc;
+ MCFGPIO_PUAPAR |= 0x03;
+ break;
+ case 1:
+ MCFGPIO_PUAPAR &= 0xF3;
+ MCFGPIO_PUAPAR |= 0x0C;
+ break;
+ case 2:
+ MCFGPIO_PASPAR &= 0xFF0F;
+ MCFGPIO_PASPAR |= 0x00A0;
+ break;
+ }
+}
#endif
#if defined(CONFIG_M5249)
@@ -369,7 +392,7 @@ int cpu_init_r (void)
* initialize a bunch of registers,
* initialize the UPM's
*/
-void cpu_init_f (void)
+void cpu_init_f(void)
{
#ifndef CFG_PLL_BYPASS
/*
@@ -379,23 +402,23 @@ void cpu_init_f (void)
volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR);
unsigned long pllcr;
#ifdef CFG_FAST_CLK
- pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
+ pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */
#else
- pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
+ pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */
#endif
- cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
- mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
- mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
- pllcr ^= 0x00000001; /* Set pll bypass to 1 */
- mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
- udelay(0x20); /* Wait for a lock ... */
-#endif /* #ifndef CFG_PLL_BYPASS */
+ cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */
+ mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */
+ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */
+ pllcr ^= 0x00000001; /* Set pll bypass to 1 */
+ mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */
+ udelay(0x20); /* Wait for a lock ... */
+#endif /* #ifndef CFG_PLL_BYPASS */
/*
* NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
- * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
- * which is their primary function.
- * ~Jeremy
+ * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
+ * which is their primary function.
+ * ~Jeremy
*/
mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
@@ -411,7 +434,7 @@ void cpu_init_f (void)
* ~Jeremy
*
*/
- mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
+ mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
mbar_writeByte(MCFSIM_SYPCR, 0x00);
mbar_writeByte(MCFSIM_SWIVR, 0x0f);
mbar_writeByte(MCFSIM_SWSR, 0x00);
@@ -431,7 +454,7 @@ void cpu_init_f (void)
mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
- mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
+ mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
/* Setup interrupt priorities for gpio7 */
/* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
@@ -459,8 +482,19 @@ void cpu_init_f (void)
/*
* initialize higher level parts of CPU like timers
*/
-int cpu_init_r (void)
+int cpu_init_r(void)
{
return (0);
}
-#endif /* #if defined(CONFIG_M5249) */
+
+void uart_port_conf(void)
+{
+ /* Setup Ports: */
+ switch (CFG_UART_PORT) {
+ case 0:
+ break;
+ case 1:
+ break;
+ }
+}
+#endif /* #if defined(CONFIG_M5249) */