Merge branch 'fixes' into cleanups

Conflicts:

	board/atmel/atngw100/atngw100.c
	board/atmel/atstk1000/atstk1000.c
	cpu/at32ap/at32ap700x/gpio.c
	include/asm-avr32/arch-at32ap700x/clk.h
	include/configs/atngw100.h
	include/configs/atstk1002.h
	include/configs/atstk1003.h
	include/configs/atstk1004.h
	include/configs/atstk1006.h
	include/configs/favr-32-ezkit.h
	include/configs/hammerhead.h
	include/configs/mimc200.h

7 files changed, 594 insertions, 67 deletions

diff --git a/cpu/mcf5227x/Makefile b/cpu/mcf5227x/Makefile
index d0e9b45..44f9385 100644
--- a/cpu/mcf5227x/Makefile
+++ b/cpu/mcf5227x/Makefile
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o cpu_init.o interrupts.o
+COBJS	= cpu.o speed.o cpu_init.o interrupts.o dspi.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mcf5227x/cpu.c b/cpu/mcf5227x/cpu.c
index 5792a1c..d9f5f43 100644
--- a/cpu/mcf5227x/cpu.c
+++ b/cpu/mcf5227x/cpu.c
@@ -60,15 +60,17 @@ int checkcpu(void)
 	}
 
 	if (id) {
+		char buf1[32], buf2[32], buf3[32];
+
 		printf("Freescale MCF%d (Mask:%01x Version:%x)\n", id, msk,
 		       ver);
-		printf("       CPU CLK %d Mhz BUS CLK %d Mhz FLB CLK %d Mhz\n",
-		       (int)(gd->cpu_clk / 1000000),
-		       (int)(gd->bus_clk / 1000000),
-		       (int)(gd->flb_clk / 1000000));
-		printf("       INP CLK %d Mhz VCO CLK %d Mhz\n",
-		       (int)(gd->inp_clk / 1000000),
-		       (int)(gd->vco_clk / 1000000));
+		printf("       CPU CLK %s MHz BUS CLK %s MHz FLB CLK %s MHz\n",
+		       strmhz(buf1, gd->cpu_clk),
+		       strmhz(buf2, gd->bus_clk),
+		       strmhz(buf3, gd->flb_clk));
+		printf("       INP CLK %s MHz VCO CLK %s MHz\n",
+		       strmhz(buf1, gd->inp_clk),
+		       strmhz(buf2, gd->vco_clk));
 	}
 
 	return 0;
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c
index cf29559..8945ef3 100644
--- a/cpu/mcf5227x/cpu_init.c
+++ b/cpu/mcf5227x/cpu_init.c
@@ -45,6 +45,7 @@ void cpu_init_f(void)
 	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
 	volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
 
+#if !defined(CONFIG_CF_SBF)
 	/* Workaround, must place before fbcs */
 	pll->psr = 0x12;
 
@@ -58,40 +59,47 @@ void cpu_init_f(void)
 	scm1->pacrg = 0;
 	scm1->pacri = 0;
 
-#if (defined(CFG_CS0_BASE) && defined(CFG_CS0_MASK) && defined(CFG_CS0_CTRL))
-	fbcs->csar0 = CFG_CS0_BASE;
-	fbcs->cscr0 = CFG_CS0_CTRL;
-	fbcs->csmr0 = CFG_CS0_MASK;
+#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
+     && defined(CONFIG_SYS_CS0_CTRL))
+	fbcs->csar0 = CONFIG_SYS_CS0_BASE;
+	fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
+	fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
 #endif
+#endif				/* CONFIG_CF_SBF */
 
-#if (defined(CFG_CS1_BASE) && defined(CFG_CS1_MASK) && defined(CFG_CS1_CTRL))
-	fbcs->csar1 = CFG_CS1_BASE;
-	fbcs->cscr1 = CFG_CS1_CTRL;
-	fbcs->csmr1 = CFG_CS1_MASK;
+#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
+     && defined(CONFIG_SYS_CS1_CTRL))
+	fbcs->csar1 = CONFIG_SYS_CS1_BASE;
+	fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
+	fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
 #endif
 
-#if (defined(CFG_CS2_BASE) && defined(CFG_CS2_MASK) && defined(CFG_CS2_CTRL))
-	fbcs->csar2 = CFG_CS2_BASE;
-	fbcs->cscr2 = CFG_CS2_CTRL;
-	fbcs->csmr2 = CFG_CS2_MASK;
+#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
+     && defined(CONFIG_SYS_CS2_CTRL))
+	fbcs->csar2 = CONFIG_SYS_CS2_BASE;
+	fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
+	fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
 #endif
 
-#if (defined(CFG_CS3_BASE) && defined(CFG_CS3_MASK) && defined(CFG_CS3_CTRL))
-	fbcs->csar3 = CFG_CS3_BASE;
-	fbcs->cscr3 = CFG_CS3_CTRL;
-	fbcs->csmr3 = CFG_CS3_MASK;
+#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
+     && defined(CONFIG_SYS_CS3_CTRL))
+	fbcs->csar3 = CONFIG_SYS_CS3_BASE;
+	fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
+	fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
 #endif
 
-#if (defined(CFG_CS4_BASE) && defined(CFG_CS4_MASK) && defined(CFG_CS4_CTRL))
-	fbcs->csar4 = CFG_CS4_BASE;
-	fbcs->cscr4 = CFG_CS4_CTRL;
-	fbcs->csmr4 = CFG_CS4_MASK;
+#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
+     && defined(CONFIG_SYS_CS4_CTRL))
+	fbcs->csar4 = CONFIG_SYS_CS4_BASE;
+	fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
+	fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
 #endif
 
-#if (defined(CFG_CS5_BASE) && defined(CFG_CS5_MASK) && defined(CFG_CS5_CTRL))
-	fbcs->csar5 = CFG_CS5_BASE;
-	fbcs->cscr5 = CFG_CS5_CTRL;
-	fbcs->csmr5 = CFG_CS5_MASK;
+#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
+     && defined(CONFIG_SYS_CS5_CTRL))
+	fbcs->csar5 = CONFIG_SYS_CS5_BASE;
+	fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
+	fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
 #endif
 
 #ifdef CONFIG_FSL_I2C
@@ -107,12 +115,12 @@ void cpu_init_f(void)
 int cpu_init_r(void)
 {
 #ifdef CONFIG_MCFRTC
-	volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
+	volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
 	volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
-	u32 oscillator = CFG_RTC_OSCILLATOR;
+	u32 oscillator = CONFIG_SYS_RTC_OSCILLATOR;
 
-	rtcex->gocu = (CFG_RTC_OSCILLATOR >> 16) & 0xFFFF;
-	rtcex->gocl = CFG_RTC_OSCILLATOR & 0xFFFF;
+	rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
+	rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
 #endif
 
 	return (0);
@@ -123,7 +131,7 @@ void uart_port_conf(void)
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
 	/* Setup Ports: */
-	switch (CFG_UART_PORT) {
+	switch (CONFIG_SYS_UART_PORT) {
 	case 0:
 		gpio->par_uart &=
 		    (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);
diff --git a/cpu/mcf5227x/dspi.c b/cpu/mcf5227x/dspi.c
new file mode 100644
index 0000000..7f48f91
--- /dev/null
+++ b/cpu/mcf5227x/dspi.c
@@ -0,0 +1,261 @@
+/*
+ *
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <malloc.h>
+
+#if defined(CONFIG_CF_DSPI)
+#include <asm/immap.h>
+
+void dspi_init(void)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+	gpio->par_dspi =
+	    GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
+	    GPIO_PAR_DSPI_SCK_SCK;
+
+	dspi->dmcr = DSPI_DMCR_MSTR | DSPI_DMCR_CSIS7 | DSPI_DMCR_CSIS6 |
+	    DSPI_DMCR_CSIS5 | DSPI_DMCR_CSIS4 | DSPI_DMCR_CSIS3 |
+	    DSPI_DMCR_CSIS2 | DSPI_DMCR_CSIS1 | DSPI_DMCR_CSIS0 |
+	    DSPI_DMCR_CRXF | DSPI_DMCR_CTXF;
+
+#ifdef CONFIG_SYS_DSPI_DCTAR0
+	dspi->dctar0 = CONFIG_SYS_DSPI_DCTAR0;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR1
+	dspi->dctar1 = CONFIG_SYS_DSPI_DCTAR1;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR2
+	dspi->dctar2 = CONFIG_SYS_DSPI_DCTAR2;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR3
+	dspi->dctar3 = CONFIG_SYS_DSPI_DCTAR3;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR4
+	dspi->dctar4 = CONFIG_SYS_DSPI_DCTAR4;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR5
+	dspi->dctar5 = CONFIG_SYS_DSPI_DCTAR5;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR6
+	dspi->dctar6 = CONFIG_SYS_DSPI_DCTAR6;
+#endif
+#ifdef CONFIG_SYS_DSPI_DCTAR7
+	dspi->dctar7 = CONFIG_SYS_DSPI_DCTAR7;
+#endif
+}
+
+void dspi_tx(int chipsel, u8 attrib, u16 data)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+	while ((dspi->dsr & 0x0000F000) >= 4) ;
+
+	dspi->dtfr = (attrib << 24) | ((1 << chipsel) << 16) | data;
+}
+
+u16 dspi_rx(void)
+{
+	volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
+
+	while ((dspi->dsr & 0x000000F0) == 0) ;
+
+	return (dspi->drfr & 0xFFFF);
+}
+
+#if defined(CONFIG_CMD_SPI)
+void spi_init_f(void)
+{
+}
+
+void spi_init_r(void)
+{
+}
+
+void spi_init(void)
+{
+	dspi_init();
+}
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+				  unsigned int max_hz, unsigned int mode)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+	struct spi_slave *slave;
+
+	slave = malloc(sizeof(struct spi_slave));
+	if (!slave)
+		return NULL;
+
+	switch (cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
+		break;
+	}
+
+	slave->bus = bus;
+	slave->cs = cs;
+
+	return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+
+	switch (slave->cs) {
+	case 0:
+		gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
+		break;
+	case 2:
+		gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK;
+		break;
+	}
+
+	free(slave);
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+	return 0;
+}
+
+void spi_release_bus(struct spi_slave *slave)
+{
+}
+
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
+	     void *din, unsigned long flags)
+{
+	static int bWrite = 0;
+	u8 *spi_rd, *spi_wr;
+	int len = bitlen >> 3;
+
+	spi_rd = (u8 *) din;
+	spi_wr = (u8 *) dout;
+
+	/* command handling */
+	if (((len == 4) || (len == 1) || (len == 5)) && (dout != NULL)) {
+		switch (*spi_wr) {
+		case 0x02:	/* Page Prog */
+			bWrite = 1;
+			dspi_tx(slave->cs, 0x80, spi_wr[0]);
+			dspi_rx();
+			dspi_tx(slave->cs, 0x80, spi_wr[1]);
+			dspi_rx();
+			dspi_tx(slave->cs, 0x80, spi_wr[2]);
+			dspi_rx();
+			dspi_tx(slave->cs, 0x80, spi_wr[3]);
+			dspi_rx();
+			return 0;
+		case 0x05:	/* Read Status */
+			if (len == 4)
+				if ((spi_wr[1] == 0xFF) && (spi_wr[2] == 0xFF)
+				    && (spi_wr[3] == 0xFF)) {
+					dspi_tx(slave->cs, 0x80, *spi_wr);
+					dspi_rx();
+				}
+			return 0;
+		case 0x06:	/* WREN */
+			dspi_tx(slave->cs, 0x00, *spi_wr);
+			dspi_rx();
+			return 0;
+		case 0x0B:	/* Fast read */
+			if ((len == 5) && (spi_wr[4] == 0)) {
+				dspi_tx(slave->cs, 0x80, spi_wr[0]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[1]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[2]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[3]);
+				dspi_rx();
+				dspi_tx(slave->cs, 0x80, spi_wr[4]);
+				dspi_rx();
+			}
+			return 0;
+		case 0x9F:	/* RDID */
+			dspi_tx(slave->cs, 0x80, *spi_wr);
+			dspi_rx();
+			return 0;
+		case 0xD8:	/* Sector erase */
+			if (len == 4)
+				if ((spi_wr[2] == 0) && (spi_wr[3] == 0)) {
+					dspi_tx(slave->cs, 0x80, spi_wr[0]);
+					dspi_rx();
+					dspi_tx(slave->cs, 0x80, spi_wr[1]);
+					dspi_rx();
+					dspi_tx(slave->cs, 0x80, spi_wr[2]);
+					dspi_rx();
+					dspi_tx(slave->cs, 0x00, spi_wr[3]);
+					dspi_rx();
+				}
+			return 0;
+		}
+	}
+
+	if (bWrite)
+		len--;
+
+	while (len--) {
+		if (dout != NULL) {
+			dspi_tx(slave->cs, 0x80, *spi_wr);
+			dspi_rx();
+			spi_wr++;
+		}
+
+		if (din != NULL) {
+			dspi_tx(slave->cs, 0x80, 0);
+			*spi_rd = dspi_rx();
+			spi_rd++;
+		}
+	}
+
+	if (flags == SPI_XFER_END) {
+		if (bWrite) {
+			dspi_tx(slave->cs, 0x00, *spi_wr);
+			dspi_rx();
+			bWrite = 0;
+		} else {
+			dspi_tx(slave->cs, 0x00, 0);
+			dspi_rx();
+		}
+	}
+
+	return 0;
+}
+#endif				/* CONFIG_CMD_SPI */
+
+#endif				/* CONFIG_CF_DSPI */
diff --git a/cpu/mcf5227x/interrupts.c b/cpu/mcf5227x/interrupts.c
index 9572a7b..85828a6 100644
--- a/cpu/mcf5227x/interrupts.c
+++ b/cpu/mcf5227x/interrupts.c
@@ -31,7 +31,7 @@
 
 int interrupt_init(void)
 {
-	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
 	/* Make sure all interrupts are disabled */
 	intp->imrh0 |= 0xFFFFFFFF;
@@ -44,9 +44,9 @@ int interrupt_init(void)
 #if defined(CONFIG_MCFTMR)
 void dtimer_intr_setup(void)
 {
-	volatile int0_t *intp = (int0_t *) (CFG_INTR_BASE);
+	volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
 
-	intp->icr0[CFG_TMRINTR_NO] = CFG_TMRINTR_PRI;
-	intp->imrh0 &= ~CFG_TMRINTR_MASK;
+	intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
+	intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
 }
 #endif
diff --git a/cpu/mcf5227x/speed.c b/cpu/mcf5227x/speed.c
index 0baf9bc..7e385d3 100644
--- a/cpu/mcf5227x/speed.c
+++ b/cpu/mcf5227x/speed.c
@@ -90,23 +90,39 @@ int get_clocks(void)
 	int vco, temp, pcrvalue, pfdr;
 	u8 bootmode;
 
-	bootmode = (ccm->ccr & 0x000C) >> 2;
-
 	pcrvalue = pll->pcr & 0xFF0F0FFF;
 	pfdr = pcrvalue >> 24;
 
-	if (pfdr != 0x1E) {
+	if (pfdr == 0x1E)
+		bootmode = 0;	/* Normal Mode */
+
+#ifdef CONFIG_CF_SBF
+	bootmode = 3;		/* Serial Mode */
+#endif
+
+	if (bootmode == 0) {
+		/* Normal mode */
+		vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
+			/* Default value */
+			pcrvalue = (pll->pcr & 0x00FFFFFF);
+			pcrvalue |= 0x1E << 24;
+			pll->pcr = pcrvalue;
+			vco =
+			    ((pll->pcr & 0xFF000000) >> 24) *
+			    CONFIG_SYS_INPUT_CLKSRC;
+		}
+		gd->vco_clk = vco;	/* Vco clock */
+	} else if (bootmode == 3) {
 		/* serial mode */
-	} else {
-		/* Normal Mode */
-		vco = pfdr * CFG_INPUT_CLKSRC;
-		gd->vco_clk = vco;
+		vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
+		gd->vco_clk = vco;	/* Vco clock */
 	}
 
 	if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
 		/* Limp mode */
 	} else {
-		gd->inp_clk = CFG_INPUT_CLKSRC;	/* Input clock */
+		gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC;	/* Input clock */
 
 		temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
 		gd->cpu_clk = vco / temp;	/* cpu clock */
diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S
index 1b47c97..0c9c89c 100644
--- a/cpu/mcf5227x/start.S
+++ b/cpu/mcf5227x/start.S
@@ -22,6 +22,7 @@
  */
 
 #include <config.h>
+#include <timestamp.h>
 #include "version.h"
 
 #ifndef	 CONFIG_IDENT_STRING
@@ -29,9 +30,9 @@
 #endif
 
 /* last three long word reserved for cache status */
-#define ICACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 4)
-#define DCACHE_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END- 8)
-#define CACR_STATUS	(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-12)
+#define ICACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4)
+#define DCACHE_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8)
+#define CACR_STATUS	(CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12)
 
 #define _START	_start
 #define _FAULT	_fault
@@ -46,6 +47,11 @@
 	addl	#60,%sp;		/* space for 15 regs */ \
 	rte;
 
+#if defined(CONFIG_CF_SBF)
+#define ASM_DRAMINIT	(asm_dram_init - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#define ASM_SBF_IMG_HDR	(asm_sbf_img_hdr - TEXT_BASE + CONFIG_SYS_INIT_RAM_ADDR)
+#endif
+
 .text
 /*
  *	Vector table. This is used for initial platform startup.
@@ -53,8 +59,14 @@
  */
 _vectors:
 
-INITSP:		.long	0x00000000	/* Initial SP	*/
-INITPC:		.long	_START	/* Initial PC		*/
+#if defined(CONFIG_CF_SBF)
+INITSP:		.long	0		/* Initial SP	*/
+INITPC:		.long	ASM_DRAMINIT	/* Initial PC 	*/
+#else
+INITSP:		.long	0	/* Initial SP	*/
+INITPC:		.long	_START	/* Initial PC 		*/
+#endif
+
 vector02:	.long	_FAULT	/* Access Error		*/
 vector03:	.long	_FAULT	/* Address Error	*/
 vector04:	.long	_FAULT	/* Illegal Instruction	*/
@@ -83,6 +95,7 @@ vector1D:	.long	_FAULT	/* Autovector Level 5	*/
 vector1E:	.long	_FAULT	/* Autovector Level 6	*/
 vector1F:	.long	_FAULT	/* Autovector Level 7	*/
 
+#if !defined(CONFIG_CF_SBF)
 /* TRAP #0 - #15 */
 vector20_2F:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
@@ -122,9 +135,231 @@ vector192_255:
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
 .long	_FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
+#endif
 
-	.text
+#if defined(CONFIG_CF_SBF)
+	/* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */
+asm_sbf_img_hdr:
+	.long	0x00000000	/* checksum, not yet implemented */
+	.long	0x00020000	/* image length */
+	.long	TEXT_BASE	/* image to be relocated at */
+
+asm_dram_init:
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
+	movec	%d0, %RAMBAR1	/* init Rambar */
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
+	clr.l %sp@-
+
+	/* Must disable global address */
+	move.l	#0xFC008000, %a1
+	move.l	#(CONFIG_SYS_CS0_BASE), (%a1)
+	move.l	#0xFC008008, %a1
+	move.l	#(CONFIG_SYS_CS0_CTRL), (%a1)
+	move.l	#0xFC008004, %a1
+	move.l	#(CONFIG_SYS_CS0_MASK), (%a1)
+
+	/*
+	 * Dram Initialization
+	 * a1, a2, and d0
+	 */
+	/* mscr sdram */
+	move.l	#0xFC0A4074, %a1
+	move.b	#(CONFIG_SYS_SDRAM_DRV_STRENGTH), (%a1)
+	nop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#0xFC0B8110, %a1
+	move.l	#0xFC0B8114, %a2
+
+	/* calculate the size */
+	move.l	#0x13, %d1
+	move.l	#(CONFIG_SYS_SDRAM_SIZE), %d2
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	lsr.l	#1, %d2
+#endif
+
+dramsz_loop:
+	lsr.l	#1, %d2
+	add.l	#1, %d1
+	cmp.l	#1, %d2
+	bne	dramsz_loop
+
+	/* SDRAM Chip 0 and 1 */
+	move.l	#(CONFIG_SYS_SDRAM_BASE), (%a1)
+	or.l	%d1, (%a1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	move.l	#(CONFIG_SYS_SDRAM_BASE1), (%a2)
+	or.l	%d1, (%a2)
+#endif
+	nop
+
+	/* dram cfg1 and cfg2 */
+	move.l	#0xFC0B8008, %a1
+	move.l	#(CONFIG_SYS_SDRAM_CFG1), (%a1)
+	nop
+	move.l	#0xFC0B800C, %a2
+	move.l	#(CONFIG_SYS_SDRAM_CFG2), (%a2)
+	nop
+
+	move.l	#0xFC0B8000, %a1	/* Mode */
+	move.l	#0xFC0B8004, %a2	/* Ctrl */
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Issue LEMR */
+	move.l	#(CONFIG_SYS_SDRAM_MODE), (%a1)
+	nop
+	move.l	#(CONFIG_SYS_SDRAM_EMOD), (%a1)
+	nop
+
+	move.l	#1000, %d0
+wait1000:
+	nop
+	subq.l	#1, %d0
+	bne	wait1000
+
+	/* Issue PALL */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 2), (%a2)
+	nop
+
+	/* Perform two refresh cycles */
+	move.l	#(CONFIG_SYS_SDRAM_CTRL + 4), %d0
+	nop
+	move.l	%d0, (%a2)
+	move.l	%d0, (%a2)
+	nop
+
+	move.l	#(CONFIG_SYS_SDRAM_CTRL), %d0
+	and.l	#0x7FFFFFFF, %d0
+	or.l	#0x10000c00, %d0
+	move.l	%d0, (%a2)
+	nop
 
+	/*
+	 * DSPI Initialization
+	 * a0 - general, sram - 0x80008000 - 32, see M52277EVB.h
+	 * a1 - dspi status
+	 * a2 - dtfr
+	 * a3 - drfr
+	 * a4 - Dst addr
+	 */
+
+	/* Enable pins for DSPI mode - chip-selects are enabled later */
+	move.l	#0xFC0A4036, %a0
+	move.b	#0x3F, %d0
+	move.b	%d0, (%a0)
+
+	/* DSPI CS */
+#ifdef CONFIG_SYS_DSPI_CS0
+	move.b	(%a0), %d0
+	or.l	#0xC0, %d0
+	move.b	%d0, (%a0)
+#endif
+#ifdef CONFIG_SYS_DSPI_CS2
+	move.l	#0xFC0A4037, %a0
+	move.b	(%a0), %d0
+	or.l	#0x10, %d0
+	move.b	%d0, (%a0)
+#endif
+	nop
+
+	/* Configure DSPI module */
+	move.l	#0xFC05C000, %a0
+	move.l	#0x80FF0C00, (%a0)	/* Master, clear TX/RX FIFO */
+
+	move.l	#0xFC05C00C, %a0
+	move.l	#0x3E000011, (%a0)
+
+	move.l	#0xFC05C034, %a2	/* dtfr */
+	move.l	#0xFC05C03B, %a3	/* drfr */
+
+	move.l	#(ASM_SBF_IMG_HDR + 4), %a1
+	move.l	(%a1)+, %d5
+	move.l	(%a1), %a4
+
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_SBFHDR_DATA_OFFSET), %a0
+	move.l	#(CONFIG_SYS_SBFHDR_SIZE), %d4
+
+	move.l	#0xFC05C02C, %a1	/* dspi status */
+
+	/* Issue commands and address */
+	move.l	#0x8004000B, %d2	/* Fast Read Cmd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 2 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 1 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Address byte 0 */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.l	#0x80040000, %d2	/* Dummy Wr and Rd */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* Transfer serial boot header to sram */
+asm_dspi_rd_loop1:
+	move.l	#0x80040000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a0)		/* read, copy to dst */
+
+	add.l	#1, %a0			/* inc dst by 1 */
+	sub.l	#1, %d4			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop1
+
+	/* Transfer u-boot from serial flash to memory */
+asm_dspi_rd_loop2:
+	move.l	#0x80040000, %d2
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	move.b	%d1, (%a4)		/* read, copy to dst */
+
+	add.l	#1, %a4			/* inc dst by 1 */
+	sub.l	#1, %d5			/* dec cnt by 1 */
+	bne	asm_dspi_rd_loop2
+
+	move.l	#0x00040000, %d2	/* Terminate */
+	jsr	asm_dspi_wr_status
+	jsr	asm_dspi_rd_status
+
+	/* jump to memory and execute */
+	move.l	#(TEXT_BASE + 0x400), %a0
+	move.l	%a0, (%a1)
+	jmp	(%a0)
+
+asm_dspi_wr_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x0000F000, %d0
+	cmp.l	#0x00003000, %d0
+	bgt	asm_dspi_wr_status
+
+	move.l	%d2, (%a2)
+	rts
+
+asm_dspi_rd_status:
+	move.l	(%a1), %d0		/* status */
+	and.l	#0x000000F0, %d0
+	lsr.l	#4, %d0
+	cmp.l	#0, %d0
+	beq	asm_dspi_rd_status
+
+	move.b	(%a3), %d1
+	rts
+#endif			/* CONFIG_CF_SBF */
+
+	.text
+	. = 0x400
 	.globl	_start
 _start:
 	nop
@@ -132,11 +367,16 @@ _start:
 	move.w #0x2700,%sr		/* Mask off Interrupt */
 
 	/* Set vector base register at the beginning of the Flash */
-	move.l	#CFG_FLASH_BASE, %d0
+#if defined(CONFIG_CF_SBF)
+	move.l	#TEXT_BASE, %d0
+	movec	%d0, %VBR
+#else
+	move.l	#CONFIG_SYS_FLASH_BASE, %d0
 	movec	%d0, %VBR
 
-	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
 	movec	%d0, %RAMBAR1
+#endif
 
 	/* initialize general use internal ram */
 	move.l #0, %d0
@@ -156,7 +396,7 @@ _start:
 
 	/* set stackpointer to end of internal ram to get some stackspace for
 	   the first c-code */
-	move.l	#(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
+	move.l	#(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp
 	clr.l %sp@-
 
 	move.l #__got_start, %a5	/* put relocation table address to a5 */
@@ -187,7 +427,7 @@ relocate_code:
 	move.l 12(%a6), %d0		/* Save copy of Global Data pointer */
 	move.l 16(%a6), %a0		/* Save copy of Destination Address */
 
-	move.l #CFG_MONITOR_BASE, %a1
+	move.l #CONFIG_SYS_MONITOR_BASE, %a1
 	move.l #__init_end, %a2
 	move.l %a0, %a3
 
@@ -202,7 +442,7 @@ relocate_code:
  * initialization, now running from RAM.
  */
 	move.l	%a0, %a1
-	add.l	#(in_ram - CFG_MONITOR_BASE), %a1
+	add.l	#(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
 	jmp	(%a1)
 
 in_ram:
@@ -212,9 +452,9 @@ clear_bss:
 	 * Now clear BSS segment
 	 */
 	move.l	%a0, %a1
-	add.l	#(_sbss - CFG_MONITOR_BASE),%a1
+	add.l	#(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
 	move.l	%a0, %d1
-	add.l	#(_ebss - CFG_MONITOR_BASE),%d1
+	add.l	#(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
 6:
 	clr.l	(%a1)+
 	cmp.l	%a1,%d1
@@ -224,11 +464,11 @@ clear_bss:
 	 * fix got table in RAM
 	 */
 	move.l	%a0, %a1
-	add.l	#(__got_start - CFG_MONITOR_BASE),%a1
+	add.l	#(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
 	move.l	%a1,%a5			/* * fix got pointer register a5 */
 
 	move.l	%a0, %a2
-	add.l	#(__got_end - CFG_MONITOR_BASE),%a2
+	add.l	#(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
 
 7:
 	move.l	(%a1),%d1
@@ -240,7 +480,7 @@ clear_bss:
 
 	/* calculate relative jump to board_init_r in ram */
 	move.l %a0, %a1
-	add.l #(board_init_r - CFG_MONITOR_BASE), %a1
+	add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
 
 	/* set parameters for board_init_r */
 	move.l %a0,-(%sp)		/* dest_addr */
@@ -276,7 +516,7 @@ icache_enable:
 	move.l	#0x01200000, %d0	/* Invalid cache */
 	movec	%d0, %CACR
 
-	move.l	#(CFG_SDRAM_BASE + 0x1c000), %d0
+	move.l	#(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0
 	movec	%d0, %ACR0
 
 	move.l	#0x81600610, %d0	/* Enable cache */
@@ -352,6 +592,6 @@ dcache_status:
 	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
-	.ascii " (", __DATE__, " - ", __TIME__, ")"
+	.ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
 	.ascii CONFIG_IDENT_STRING, "\0"
 	.align 4