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authorWolfgang Denk <wd@denx.de>2009-04-05 23:04:30 +0200
committerWolfgang Denk <wd@denx.de>2009-04-05 23:04:30 +0200
commit712ac6a1a6909a58d6549fb220cc921a7e9f9979 (patch)
tree7391a68d2b81d9a9096e170b97bbfe0ed81c2c7f /cpu/lh7a40x
parent23e4af49e066a53cd3e3659b68ef90572d88de84 (diff)
parentc6fadb9c73a6a3e0c7f20696e978304a593a8d2d (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'cpu/lh7a40x')
-rw-r--r--cpu/lh7a40x/cpu.c121
1 files changed, 10 insertions, 111 deletions
diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c
index 8ff3a36..93ebd13 100644
--- a/cpu/lh7a40x/cpu.c
+++ b/cpu/lh7a40x/cpu.c
@@ -32,61 +32,13 @@
#include <common.h>
#include <command.h>
#include <arm920t.h>
+#include <asm/system.h>
#ifdef CONFIG_USE_IRQ
DECLARE_GLOBAL_DATA_PTR;
#endif
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
- unsigned long value;
-
- __asm__ __volatile__(
- "mrc p15, 0, %0, c1, c0, 0 @ read control reg\n"
- : "=r" (value)
- :
- : "memory");
-
-#ifdef MMU_DEBUG
- printf ("p15/c1 is = %08lx\n", value);
-#endif
- return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-#ifdef MMU_DEBUG
- printf ("write %08lx to p15/c1\n", value);
-#endif
- __asm__ __volatile__(
- "mcr p15, 0, %0, c1, c0, 0 @ write it back\n"
- :
- : "r" (value)
- : "memory");
-
- read_p15_c1 ();
-}
-
-static void cp_delay (void)
-{
- volatile int i;
-
- /* copro seems to need some delay between reading and writing */
- for (i = 0; i < 100; i++);
-}
-
-/* See also ARM Ref. Man. */
-#define C1_MMU (1<<0) /* mmu off/on */
-#define C1_ALIGN (1<<1) /* alignment faults off/on */
-#define C1_DC (1<<2) /* dcache off/on */
-#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */
-#define C1_SYS_PROT (1<<8) /* system protection */
-#define C1_ROM_PROT (1<<9) /* ROM protection */
-#define C1_IC (1<<12) /* icache off/on */
-#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */
-#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */
+static void cache_flush(void);
int cpu_init (void)
{
@@ -109,75 +61,22 @@ int cleanup_before_linux (void)
* we turn off caches etc ...
*/
- unsigned long i;
-
disable_interrupts ();
/* turn off I/D-cache */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(C1_DC | C1_IC);
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ icache_disable();
+ dcache_disable();
/* flush I/D-cache */
- i = 0;
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
- return (0);
-}
+ cache_flush();
-int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
- disable_interrupts ();
- reset_cpu (0);
- /*NOTREACHED*/
- return (0);
-}
-
-void icache_enable (void)
-{
- ulong reg;
-
- reg = read_p15_c1 ();
- cp_delay ();
- write_p15_c1 (reg | C1_IC);
-}
-
-void icache_disable (void)
-{
- ulong reg;
-
- reg = read_p15_c1 ();
- cp_delay ();
- write_p15_c1 (reg & ~C1_IC);
-}
-
-int icache_status (void)
-{
- return (read_p15_c1 () & C1_IC) != 0;
-}
-
-#ifdef USE_920T_MMU
-/* It makes no sense to use the dcache if the MMU is not enabled */
-void dcache_enable (void)
-{
- ulong reg;
-
- reg = read_p15_c1 ();
- cp_delay ();
- write_p15_c1 (reg | C1_DC);
+ return 0;
}
-void dcache_disable (void)
+/* flush I/D-cache */
+static void cache_flush (void)
{
- ulong reg;
+ unsigned long i = 0;
- reg = read_p15_c1 ();
- cp_delay ();
- reg &= ~C1_DC;
- write_p15_c1 (reg);
-}
-
-int dcache_status (void)
-{
- return (read_p15_c1 () & C1_DC) != 0;
+ asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
}
-#endif