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authorAnson Huang <b20788@freescale.com>2012-12-05 13:58:34 -0500
committerRichard Liu <r66033@freescale.com>2013-04-08 10:54:05 +0800
commit45dffc786dcb4b7910d1775f732d4da1a1d4dfc7 (patch)
tree26c6a7b2b699677c6fda4b886c43d6a12897e035 /cpu/leon2
parentd08f89b72e8fa1da798de4b0b33b2f411b85451b (diff)
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ENGR00235821 mx6: correct work flow of PFDs
PFDs need to be gate/ungate after PLL lock to reset PFDs to right state. Otherwise PFDs may lose correct state in state-machine, then no output clock. For i.MX6DL and i.MX6SL, ROM have taken care of PFD396 already since the bus clock needs it. Signed-off-by: Anson Huang <b20788@freescale.com>
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