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| author | Stefan Roese <sr@denx.de> | 2007-02-20 10:43:34 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-02-20 10:43:34 +0100 |
| commit | 4037ed3b63923cfcec27f784a89057c3cbabcedb (patch) | |
| tree | ea1ced56a2dab67f408a9cddccaf6c1d3f4100e0 /cpu/ixp/timer.c | |
| parent | 36d830c9830379045f5daa9f542ac1c990c70068 (diff) | |
| download | u-boot-imx-4037ed3b63923cfcec27f784a89057c3cbabcedb.zip u-boot-imx-4037ed3b63923cfcec27f784a89057c3cbabcedb.tar.gz u-boot-imx-4037ed3b63923cfcec27f784a89057c3cbabcedb.tar.bz2 | |
[PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM support
This patch adds support for the DDR2 controller used on the
440SP and 440SPe. It is tested on the Katmai (440SPe) eval
board and works fine with the following DIMM modules:
- Corsair CM2X512-5400C4 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM)
- Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM)
This patch also adds the nice functionality to dynamically
create the TLB entries for the SDRAM (tlb.c). So we should
never run into such problems with wrong (too short) TLB
initialization again on these platforms.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/ixp/timer.c')
0 files changed, 0 insertions, 0 deletions