Merge branch 'master' of /home/stefan/git/u-boot/u-boot

25 files changed, 65 insertions, 65 deletions

diff --git a/cpu/ixp/npe/IxEthAcc.c b/cpu/ixp/npe/IxEthAcc.c
index d981649..061b24b 100644
--- a/cpu/ixp/npe/IxEthAcc.c
+++ b/cpu/ixp/npe/IxEthAcc.c
@@ -215,7 +215,7 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
 
    if ( ! IX_ETH_ACC_IS_SERVICE_INITIALIZED() )
    {
-   	return(IX_ETH_ACC_FAIL);
+	return(IX_ETH_ACC_FAIL);
    }
 
    /*
@@ -235,8 +235,8 @@ PUBLIC IxEthAccStatus ixEthAccPortInit( IxEthAccPortId portId)
 
    if ( IX_ETH_IS_PORT_INITIALIZED(portId) )
    {
-   	/* Already initialized */
-   	return(IX_ETH_ACC_FAIL);
+	/* Already initialized */
+	return(IX_ETH_ACC_FAIL);
    }
 
    if(ixEthAccMacInit(portId)!=IX_ETH_ACC_SUCCESS)
diff --git a/cpu/ixp/npe/IxEthAccCommon.c b/cpu/ixp/npe/IxEthAccCommon.c
index bda2c44..211203d 100644
--- a/cpu/ixp/npe/IxEthAccCommon.c
+++ b/cpu/ixp/npe/IxEthAccCommon.c
@@ -96,7 +96,7 @@ extern IxEthAccInfo   ixEthAccDataInfo;
 IX_ETH_ACC_PRIVATE
 IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
   {
-    IX_ETH_ACC_RX_FRAME_ETH_Q, 	     /**< Queue ID */
+    IX_ETH_ACC_RX_FRAME_ETH_Q,	     /**< Queue ID */
     "Eth Rx Q",
     ixEthRxFrameQMCallback,          /**< Functional callback */
     (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
@@ -104,7 +104,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     TRUE,			     /**< Enable Q notification at startup */
     IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
   };
 
@@ -116,7 +116,7 @@ IxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =
 IX_ETH_ACC_PRIVATE
 IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
   {
-    IX_ETH_ACC_RX_FRAME_ETH_Q, 	     /**< Queue ID */
+    IX_ETH_ACC_RX_FRAME_ETH_Q,	     /**< Queue ID */
     "Eth Rx Q",
     ixEthRxFrameQMCallback,          /**< Functional callback */
     (IxQMgrCallbackId) 0,	     /**< Callback tag	      */
@@ -124,7 +124,7 @@ IxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     TRUE,			     /**< Enable Q notification at startup */
     IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */
   };
 
@@ -146,7 +146,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /***< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /***< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 
@@ -159,7 +159,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE,  /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 #ifdef __ixp46X
@@ -172,7 +172,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE,  /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 #endif
@@ -185,7 +185,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE,	 /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 
@@ -198,7 +198,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     FALSE,			     /**< Disable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE,	     /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */
   },
 #ifdef __ixp46X
@@ -211,7 +211,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /** Queue Entry Sizes - all Q entries are single ord entries   */
     FALSE,			     /** Disable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE,	     /** Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /* No queues use almost empty */
+    IX_QMGR_Q_WM_LEVEL0,	     /* No queues use almost empty */
     IX_QMGR_Q_WM_LEVEL64,	      /** Q High water mark - needed used  */
   },
 #endif
@@ -224,7 +224,7 @@ IxEthAccQregInfo ixEthAccQmgrStaticInfo[]=
     IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */
     TRUE,			     /**< Enable Q notification at startup */
     IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback  */
-    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */
+    IX_QMGR_Q_WM_LEVEL0,	     /**< Q Low water mark */
     IX_QMGR_Q_WM_LEVEL2,	     /**< Q High water mark - needed by NPE */
   },
 
diff --git a/cpu/ixp/npe/IxEthAccDataPlane.c b/cpu/ixp/npe/IxEthAccDataPlane.c
index e46fc9b..b62f0d0 100644
--- a/cpu/ixp/npe/IxEthAccDataPlane.c
+++ b/cpu/ixp/npe/IxEthAccDataPlane.c
@@ -544,7 +544,7 @@ ixEthAccMbufFromRxQ(IX_OSAL_MBUF *mbuf)
 	    IX_OSAL_MBUF_MLEN(ptr) = (len >> IX_ETHNPE_ACC_LENGTH_OFFSET);
 
             /* get the next pointer */
- 	    PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
+	    PTR_NPE2VIRT(IX_OSAL_MBUF *,IX_ETHACC_NE_NEXT(ptr), nextPtr);
 	    if (nextPtr != NULL)
 	    {
 		nextPtr = (IX_OSAL_MBUF *)((UINT8 *)nextPtr - offsetof(IX_OSAL_MBUF,ix_ne));
diff --git a/cpu/ixp/npe/IxEthAccMac.c b/cpu/ixp/npe/IxEthAccMac.c
index d57e716..369ee91 100644
--- a/cpu/ixp/npe/IxEthAccMac.c
+++ b/cpu/ixp/npe/IxEthAccMac.c
@@ -2423,14 +2423,14 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId)
         REG_READ(ixEthAccMacBase[portId],
 		 IX_ETH_ACC_MAC_RX_CNTRL1,
 		 regval);
- 	REG_WRITE(ixEthAccMacBase[portId],
+	REG_WRITE(ixEthAccMacBase[portId],
 		  IX_ETH_ACC_MAC_RX_CNTRL1,
 		  regval & ~IX_ETH_ACC_RX_CNTRL1_RX_EN);
 
         REG_READ(ixEthAccMacBase[portId],
 		 IX_ETH_ACC_MAC_TX_CNTRL1,
 		 regval);
- 	REG_WRITE(ixEthAccMacBase[portId],
+	REG_WRITE(ixEthAccMacBase[portId],
 		  IX_ETH_ACC_MAC_TX_CNTRL1,
 		  regval & ~IX_ETH_ACC_TX_CNTRL1_TX_EN);
     }
@@ -2493,7 +2493,7 @@ ixEthAccMacStateUpdate(IxEthAccPortId portId)
         REG_READ(ixEthAccMacBase[portId],
 		 IX_ETH_ACC_MAC_TX_CNTRL1,
 		 regval);
- 	REG_WRITE(ixEthAccMacBase[portId],
+	REG_WRITE(ixEthAccMacBase[portId],
 		  IX_ETH_ACC_MAC_TX_CNTRL1,
 		  regval | IX_ETH_ACC_TX_CNTRL1_TX_EN);
     }
diff --git a/cpu/ixp/npe/IxEthAccMii.c b/cpu/ixp/npe/IxEthAccMii.c
index 86368a4..d282aa6 100644
--- a/cpu/ixp/npe/IxEthAccMii.c
+++ b/cpu/ixp/npe/IxEthAccMii.c
@@ -324,7 +324,7 @@ ixEthAccMiiWriteRtn (UINT8 phyAddr,
 
 	/*The "GO" bit is reset to 0 when the write completes*/
 	if((regval & IX_ETH_ACC_MII_GO) == 0x0)
-	{	    	    
+	{		    
 	    break;
 	}
 	/* Sleep for a while */
diff --git a/cpu/ixp/npe/IxNpeDlImageMgr.c b/cpu/ixp/npe/IxNpeDlImageMgr.c
index 75b42f2..ccc0da7 100644
--- a/cpu/ixp/npe/IxNpeDlImageMgr.c
+++ b/cpu/ixp/npe/IxNpeDlImageMgr.c
@@ -164,7 +164,7 @@ ixNpeDlImageMgrImageIdCompare (IxNpeDlImageId *imageIdA,
 				 
 PRIVATE BOOL
 ixNpeDlImageMgrNpeFunctionIdCompare (IxNpeDlImageId *imageIdA,
-    				       IxNpeDlImageId *imageIdB);
+				       IxNpeDlImageId *imageIdB);
 
 #if 0
 PRIVATE IX_STATUS
diff --git a/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c b/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c
index 9dcf3c1..18cac50 100644
--- a/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c
+++ b/cpu/ixp/npe/IxNpeDlNpeMgrUtils.c
@@ -613,9 +613,9 @@ ixNpeDlNpeMgrLogicalRegWrite (
 
     if (verify)
     {
-    	status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
-    						   regSize, ctxtNum, &retRegVal);
-    						   
+	status = ixNpeDlNpeMgrLogicalRegRead (npeBaseAddress, regAddr,
+						   regSize, ctxtNum, &retRegVal);
+						   
         if (IX_SUCCESS == status)
         {
             if (regVal != retRegVal)
diff --git a/cpu/ixp/npe/IxOsalIoMem.c b/cpu/ixp/npe/IxOsalIoMem.c
index 9e540c1..34df92b 100644
--- a/cpu/ixp/npe/IxOsalIoMem.c
+++ b/cpu/ixp/npe/IxOsalIoMem.c
@@ -281,7 +281,7 @@ ixOsalIoMemUnmap (UINT32 requestedAddress, UINT32 endianType)
  * Return value: corresponding physical address, or NULL 
  *               if there is no physical address addressable 
  *               by the given virtual address
- * OS: 	VxWorks, Linux, WinCE, QNX, eCos
+ * OS:	VxWorks, Linux, WinCE, QNX, eCos
  * Reentrant: Yes
  * IRQ safe: Yes
  */
@@ -310,7 +310,7 @@ ixOsalIoMemVirtToPhys (UINT32 virtualAddress, UINT32 requestedCoherency)
  * Return value: corresponding physical address, or NULL 
  *               if there is no physical address addressable 
  *               by the given virtual address
- * OS: 	VxWorks, Linux, WinCE, QNX, eCos
+ * OS:	VxWorks, Linux, WinCE, QNX, eCos
  * Reentrant: Yes
  * IRQ safe: Yes
  */
diff --git a/cpu/ixp/npe/IxQMgrAqmIf.c b/cpu/ixp/npe/IxQMgrAqmIf.c
index b27b3a2..7386513 100644
--- a/cpu/ixp/npe/IxQMgrAqmIf.c
+++ b/cpu/ixp/npe/IxQMgrAqmIf.c
@@ -209,7 +209,7 @@ ixQMgrAqmIfInit (void)
 	 */
 
 	/* AQM Queue access reg addresses, per queue */
-   	ixQMgrAqmIfQueAccRegAddr[i] = 
+	ixQMgrAqmIfQueAccRegAddr[i] = 
 	    (UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
 	ixQMgrQInlinedReadWriteInfo[i].qAccRegAddr = 
 	    (volatile UINT32 *)(aqmBaseAddress + IX_QMGR_Q_ACCESS_ADDR_GET(i));
diff --git a/cpu/ixp/npe/IxQMgrQAccess.c b/cpu/ixp/npe/IxQMgrQAccess.c
index 2c3e302..8885736 100644
--- a/cpu/ixp/npe/IxQMgrQAccess.c
+++ b/cpu/ixp/npe/IxQMgrQAccess.c
@@ -360,7 +360,7 @@ ixQMgrQNumEntriesGet (IxQMgrQId qId,
 	    }
 	    else
 	    {
-  	       /* The queue is either empty, either moving,
+	       /* The queue is either empty, either moving,
 	        * Client can retry if they wish
 	        */
 		*numEntriesPtr = 0;
diff --git a/cpu/ixp/npe/include/IxDmaAcc.h b/cpu/ixp/npe/include/IxDmaAcc.h
index 53d2625..45c7527 100644
--- a/cpu/ixp/npe/include/IxDmaAcc.h
+++ b/cpu/ixp/npe/include/IxDmaAcc.h
@@ -172,7 +172,7 @@ typedef UINT32 IxDmaAccRequestId;
 #define IX_DMA_REQUEST_FULL 16
 
 /**
- * @ingroup 	IxDmaAcc
+ * @ingroup	IxDmaAcc
  * @brief       DMA completion notification
  * This function is called to notify a client that the DMA has been completed
  * @param status @ref IxDmaReturnStatus [out] - reporting to client
@@ -181,11 +181,11 @@ typedef UINT32 IxDmaAccRequestId;
 typedef void (*IxDmaAccDmaCompleteCallback) (IxDmaReturnStatus status);
 
 /**
- * @ingroup 	IxDmaAcc
+ * @ingroup	IxDmaAcc
  * 
  * @fn ixDmaAccInit(IxNpeDlNpeId npeId)
  * 
- * @brief 	Initialise the DMA Access component
+ * @brief	Initialise the DMA Access component
  * This function will initialise the DMA Access component internals
  * @param npeId @ref IxNpeDlNpeId [in] - NPE to use for Dma Transfer
  * @return @li IX_SUCCESS succesfully initialised the component
@@ -196,7 +196,7 @@ PUBLIC IX_STATUS
 ixDmaAccInit(IxNpeDlNpeId npeId);
 
 /**
- * @ingroup 	IxDmaAcc
+ * @ingroup	IxDmaAcc
  * 
  * @fn ixDmaAccDmaTransfer(
     IxDmaAccDmaCompleteCallback callback,
@@ -225,8 +225,8 @@ ixDmaAccInit(IxNpeDlNpeId npeId);
  * @param AddressingMode @ref IxDmaAddressingMode [in] - The DMA addressing mode
  * @param TransferWidth	@ref IxDmaTransferWidth [in] - The DMA transfer width
  *
- * @return @li IX_DMA_SUCCESS 	Notification that the DMA request is succesful
- * @return @li IX_DMA_FAIL 	IxDmaAcc not yet initialised or some internal error has occured
+ * @return @li IX_DMA_SUCCESS	Notification that the DMA request is succesful
+ * @return @li IX_DMA_FAIL	IxDmaAcc not yet initialised or some internal error has occured
  * @return @li IX_DMA_INVALID_TRANSFER_WIDTH Transfer width is nit valid
  * @return @li IX_DMA_INVALID_TRANSFER_LENGTH Transfer length outside of valid range
  * @return @li IX_DMA_INVALID_TRANSFER_MODE Transfer Mode not valid
diff --git a/cpu/ixp/npe/include/IxEthAcc.h b/cpu/ixp/npe/include/IxEthAcc.h
index b424648..ff706c4 100644
--- a/cpu/ixp/npe/include/IxEthAcc.h
+++ b/cpu/ixp/npe/include/IxEthAcc.h
@@ -626,8 +626,8 @@ PUBLIC void ixEthAccUnload(void);
  *   required features.
  *
  * Dependant on Services: (Must be initialized before using this service may be initialized)
- * 	ixNPEmh - NPE Message handling service.
- * 	ixQmgr	- Queue Manager component.
+ *	ixNPEmh - NPE Message handling service.
+ *	ixQmgr	- Queue Manager component.
  *
  * @param portId  @ref IxEthAccPortId [in]
  *
@@ -745,7 +745,7 @@ typedef void (*IxEthAccPortTxDoneCallback) ( UINT32 callbackTag, IX_OSAL_MBUF *b
  *
  * @fn ixEthAccPortTxDoneCallbackRegister( IxEthAccPortId portId, 
 					   IxEthAccPortTxDoneCallback txCallbackFn, 
- 					   UINT32 callbackTag)
+					   UINT32 callbackTag)
  *
  * @brief Register a callback function to allow 
  * the transmitted buffers to return to the user.
diff --git a/cpu/ixp/npe/include/IxEthAccMii_p.h b/cpu/ixp/npe/include/IxEthAccMii_p.h
index aa42f9c..568d4a0 100644
--- a/cpu/ixp/npe/include/IxEthAccMii_p.h
+++ b/cpu/ixp/npe/include/IxEthAccMii_p.h
@@ -81,13 +81,13 @@
 #define IX_ETH_ACC_MII_STAT_REG	    0x1	/* Status Register */
 #define IX_ETH_ACC_MII_PHY_ID1_REG  0x2	/* PHY identifier 1 Register */
 #define IX_ETH_ACC_MII_PHY_ID2_REG  0x3	/* PHY identifier 2 Register */
-#define IX_ETH_ACC_MII_AN_ADS_REG   0x4	/* Auto-Negotiation 	  */
+#define IX_ETH_ACC_MII_AN_ADS_REG   0x4	/* Auto-Negotiation	  */
 					/* Advertisement Register */
-#define IX_ETH_ACC_MII_AN_PRTN_REG  0x5	/* Auto-Negotiation 	    */
+#define IX_ETH_ACC_MII_AN_PRTN_REG  0x5	/* Auto-Negotiation	    */
 					/* partner ability Register */
 #define IX_ETH_ACC_MII_AN_EXP_REG   0x6	/* Auto-Negotiation   */
 					/* Expansion Register */
-#define IX_ETH_ACC_MII_AN_NEXT_REG  0x7	/* Auto-Negotiation 	       */
+#define IX_ETH_ACC_MII_AN_NEXT_REG  0x7	/* Auto-Negotiation	       */
 					/* next-page transmit Register */
 
 IxEthAccStatus ixEthAccMdioShow (void);
diff --git a/cpu/ixp/npe/include/IxEthAcc_p.h b/cpu/ixp/npe/include/IxEthAcc_p.h
index 37c5560..0ee4123 100644
--- a/cpu/ixp/npe/include/IxEthAcc_p.h
+++ b/cpu/ixp/npe/include/IxEthAcc_p.h
@@ -262,7 +262,7 @@ typedef struct
 {
   IxEthAccPortTxDoneCallback  txBufferDoneCallbackFn;
   UINT32  txCallbackTag;
-  IxEthAccDataPlaneQList 	txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
+  IxEthAccDataPlaneQList	txQ[IX_ETH_ACC_NUM_TX_PRIORITIES]; /**< Transmit Q */
   IxEthAccSchedulerDiscipline schDiscipline; /**< Transmit Xscale QoS */
   IxQMgrQId txQueue; /**< txQueue for this port */
   IxEthAccTxDataStats stats; /**< Transmit s/w stats */
diff --git a/cpu/ixp/npe/include/IxEthMii.h b/cpu/ixp/npe/include/IxEthMii.h
index a1bfe06..397253a 100644
--- a/cpu/ixp/npe/include/IxEthMii.h
+++ b/cpu/ixp/npe/include/IxEthMii.h
@@ -106,9 +106,9 @@ PUBLIC IX_STATUS ixEthMiiPhyScan(BOOL phyPresent[], UINT32 maxPhyCount);
  * @ingroup IxEthMii
  *
  * @fn ixEthMiiPhyConfig(UINT32 phyAddr,
-   		         BOOL speed100, 
- 			 BOOL fullDuplex, 
- 			 BOOL autonegotiate)
+		         BOOL speed100, 
+			 BOOL fullDuplex, 
+			 BOOL autonegotiate)
  *
  *
  * @brief Configure a PHY
@@ -209,10 +209,10 @@ PUBLIC IX_STATUS ixEthMiiPhyReset(UINT32 phyAddr);
  * @ingroup IxEthMii
  *
  * @fn ixEthMiiLinkStatus(UINT32 phyAddr, 
- 			  BOOL *linkUp,
- 			  BOOL *speed100, 
- 			  BOOL *fullDuplex,
- 		          BOOL *autoneg)
+			  BOOL *linkUp,
+			  BOOL *speed100, 
+			  BOOL *fullDuplex,
+		          BOOL *autoneg)
  *
  * @brief Retrieve the current status of a PHY
  *   Retrieve the link, speed, duplex and autonegotiation status of a PHY
diff --git a/cpu/ixp/npe/include/IxI2cDrv.h b/cpu/ixp/npe/include/IxI2cDrv.h
index 2472f31..92c6b24 100644
--- a/cpu/ixp/npe/include/IxI2cDrv.h
+++ b/cpu/ixp/npe/include/IxI2cDrv.h
@@ -64,8 +64,8 @@
 /**
  * @ingroup IxI2cDrv
  * @brief The interval of micro/mili seconds the IXP will wait before it polls for
- * 			status from the ixI2cIntrXferStatus; Every 20us is 1 byte @
- * 			400Kbps and 4 bytes	@ 100Kbps. This is dependent on delay type selected
+ *			status from the ixI2cIntrXferStatus; Every 20us is 1 byte @
+ *			400Kbps and 4 bytes	@ 100Kbps. This is dependent on delay type selected
  *          through the API ixI2cDrvDelayTypeSelect.
  */
 #define IX_I2C_US_POLL_FOR_XFER_STATUS	20
diff --git a/cpu/ixp/npe/include/IxOsalAssert.h b/cpu/ixp/npe/include/IxOsalAssert.h
index 45cebcd..04a4f51 100644
--- a/cpu/ixp/npe/include/IxOsalAssert.h
+++ b/cpu/ixp/npe/include/IxOsalAssert.h
@@ -1,6 +1,6 @@
 /*
  * @file        IxOsalAssert.h 
- * @author 	Intel Corporation
+ * @author	Intel Corporation
  * @date        25-08-2004
  *
  * @brief       description goes here
diff --git a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h
index 5ac3f0c..4cf80d3 100644
--- a/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h
+++ b/cpu/ixp/npe/include/IxOsalBackwardBufferMgt.h
@@ -76,7 +76,7 @@ typedef IX_OSAL_MBUF_POOL IX_MBUF_POOL;
 #define IX_MBUF_MTYPE(m_blk_ptr) \
                 IX_OSAL_MBUF_MTYPE(m_blk_ptr)
 
-#define IX_MBUF_FLAGS(m_blk_ptr)   	\
+#define IX_MBUF_FLAGS(m_blk_ptr)	\
 		IX_OSAL_MBUF_FLAGS(m_blk_ptr)
 
 
diff --git a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h
index 18f8f24..3881a3b 100644
--- a/cpu/ixp/npe/include/IxOsalBackwardMemMap.h
+++ b/cpu/ixp/npe/include/IxOsalBackwardMemMap.h
@@ -136,6 +136,6 @@
 
 #define IX_OSSERV_MEM_MAP(physAddr, size)		IX_OSAL_MEM_MAP(physAddr, size)
 
-#define IX_OSSERV_MEM_UNMAP(virtAddr) 			IX_OSAL_MEM_UNMAP(virtAddr)
+#define IX_OSSERV_MEM_UNMAP(virtAddr)			IX_OSAL_MEM_UNMAP(virtAddr)
 
 #endif /* IX_OSAL_BACKWARD_MEM_MAP_H */
diff --git a/cpu/ixp/npe/include/IxOsalIoMem.h b/cpu/ixp/npe/include/IxOsalIoMem.h
index ac0ce65..ea6d64d 100644
--- a/cpu/ixp/npe/include/IxOsalIoMem.h
+++ b/cpu/ixp/npe/include/IxOsalIoMem.h
@@ -1,6 +1,6 @@
 /*
  * @file        IxOsalIoMem.h
- * @author 	Intel Corporation
+ * @author	Intel Corporation
  * @date        25-08-2004
  *
  * @brief       description goes here
diff --git a/cpu/ixp/npe/include/IxOsalMemAccess.h b/cpu/ixp/npe/include/IxOsalMemAccess.h
index 2ad0ccf..9e7fb87 100644
--- a/cpu/ixp/npe/include/IxOsalMemAccess.h
+++ b/cpu/ixp/npe/include/IxOsalMemAccess.h
@@ -410,7 +410,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
 #define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_BE(wAddr) 
 #define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_BE(sAddr) 
 #define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_BE(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData) 	IX_OSAL_WRITE_LONG_BE(wAddr, wData)
+#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_BE(wAddr, wData)
 #define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_BE(sAddr, sData)
 #define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_BE(bAddr, bData)
 
@@ -419,7 +419,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
 #define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_AC(wAddr) 
 #define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_LE_AC(sAddr) 
 #define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_LE_AC(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData) 	IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
+#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_LE_AC(wAddr, wData)
 #define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_LE_AC(sAddr, sData)
 #define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_LE_AC(bAddr, bData)
 
@@ -428,7 +428,7 @@ ixOsalDataCoherentShortWriteSwap (volatile UINT16 * sAddr, UINT16 sData)
 #define IX_OSAL_READ_LONG(wAddr)            IX_OSAL_READ_LONG_LE_DC(wAddr) 
 #define IX_OSAL_READ_SHORT(sAddr)	        IX_OSAL_READ_SHORT_LE_DC(sAddr) 
 #define IX_OSAL_READ_BYTE(bAddr)	        IX_OSAL_READ_BYTE_LE_DC(bAddr) 
-#define IX_OSAL_WRITE_LONG(wAddr, wData) 	IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
+#define IX_OSAL_WRITE_LONG(wAddr, wData)	IX_OSAL_WRITE_LONG_LE_DC(wAddr, wData)
 #define IX_OSAL_WRITE_SHORT(sAddr, sData)	IX_OSAL_WRITE_SHORT_LE_DC(sAddr, sData)
 #define IX_OSAL_WRITE_BYTE(bAddr, bData)	IX_OSAL_WRITE_BYTE_LE_DC(bAddr, bData)
 
diff --git a/cpu/ixp/npe/include/IxOsalTypes.h b/cpu/ixp/npe/include/IxOsalTypes.h
index c617ec5..a190a70 100644
--- a/cpu/ixp/npe/include/IxOsalTypes.h
+++ b/cpu/ixp/npe/include/IxOsalTypes.h
@@ -175,7 +175,7 @@ typedef volatile INT32 VINT32;
 
 
 #ifndef __inline__
-#define __inline__ 	IX_OSAL_INLINE
+#define __inline__	IX_OSAL_INLINE
 #endif
 
 
diff --git a/cpu/ixp/npe/include/IxQMgr.h b/cpu/ixp/npe/include/IxQMgr.h
index c083a2b..165ed96 100644
--- a/cpu/ixp/npe/include/IxQMgr.h
+++ b/cpu/ixp/npe/include/IxQMgr.h
@@ -1134,7 +1134,7 @@ ixQMgrQRead (IxQMgrQId qId,
 	 * day scenario there are many entries in the queue
 	 * and the counter does not reach zero.
 	 */
- 	if (infoPtr->qReadCount-- == 0)
+	if (infoPtr->qReadCount-- == 0)
 	{
 	    /* There is maybe no entry in the queue
 	     * qReadCount is now negative, but will be corrected before
@@ -1475,7 +1475,7 @@ ixQMgrQWrite (IxQMgrQId qId,
 	    ++entry;
 	    IX_QMGR_INLINE_WRITE_LONG(++qAccRegAddr, *entry);
 	}
- 	entrySize = infoPtr->qEntrySizeInWords;
+	entrySize = infoPtr->qEntrySizeInWords;
     }
 
     /* overflow is available for lower queues only */
diff --git a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h
index 7f5733c..4f0f64d 100644
--- a/cpu/ixp/npe/include/IxQMgrAqmIf_p.h
+++ b/cpu/ixp/npe/include/IxQMgrAqmIf_p.h
@@ -498,7 +498,7 @@ ixQMgrAqmIfQPop (IxQMgrQId qId,
     volatile UINT32 *accRegAddr;
 
     accRegAddr = (UINT32*)(aqmBaseAddress +
-    			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
+			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
 
     switch (numWords)
     {
@@ -533,7 +533,7 @@ ixQMgrAqmIfQPush (IxQMgrQId qId,
     volatile UINT32 *accRegAddr;
 
     accRegAddr = (UINT32*)(aqmBaseAddress +
-    			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
+			   IX_QMGR_Q_ACCESS_ADDR_GET(qId));
     
     switch (numWords)
     {
@@ -683,9 +683,9 @@ ixQMgrAqmIfRegisterBitCheck (IxQMgrQId qId,
      * multiple queues split accross registers
      */
     registerAddress = (UINT32*)(aqmBaseAddress +
-    				registerBaseAddrOffset +
-    				((qId / queuesPerRegWord) *
-    				 IX_QMGR_NUM_BYTES_PER_WORD));
+				registerBaseAddrOffset +
+				((qId / queuesPerRegWord) *
+				 IX_QMGR_NUM_BYTES_PER_WORD));
 
     /*
      * Get the status word
diff --git a/cpu/ixp/npe/include/IxQueueAssignments.h b/cpu/ixp/npe/include/IxQueueAssignments.h
index 0c1543f..f7194e7 100644
--- a/cpu/ixp/npe/include/IxQueueAssignments.h
+++ b/cpu/ixp/npe/include/IxQueueAssignments.h
@@ -409,7 +409,7 @@
 * @note THIS IS NOT USED - the Rx queues are read from EthDB QoS configuration
 * 
 */
-#define IX_ETH_ACC_RX_FRAME_ETH_Q 	(IX_QMGR_QUEUE_4)
+#define IX_ETH_ACC_RX_FRAME_ETH_Q	(IX_QMGR_QUEUE_4)
 
 /**
 *