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authorWolfgang Denk <wd@castor.denx.de>2006-05-30 15:56:48 +0200
committerWolfgang Denk <wd@castor.denx.de>2006-05-30 15:56:48 +0200
commitba94a1bba3600d387edba7eb451990d9891e1c2f (patch)
treee84f737ac88e15342b4cab23c9e631987e8ee75e /cpu/ixp/npe/include/IxOsalOs.h
parent5770a1e488621a9e7e344afed7c921ff4e715a63 (diff)
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* Update Intel IXP4xx support
- Add IXP4xx NPE ethernet MAC support - Add support for Intel IXDPG425 board - Add support for Prodrive PDNB3 board - Add IRQ support Patch by Stefan Roese, 23 May 2006 [This patch does not include cpu/ixp/npe/IxNpeMicrocode.c which still sufferes from licensing issues. Blame Intel.]
Diffstat (limited to 'cpu/ixp/npe/include/IxOsalOs.h')
-rw-r--r--cpu/ixp/npe/include/IxOsalOs.h30
1 files changed, 30 insertions, 0 deletions
diff --git a/cpu/ixp/npe/include/IxOsalOs.h b/cpu/ixp/npe/include/IxOsalOs.h
new file mode 100644
index 0000000..6c66613
--- /dev/null
+++ b/cpu/ixp/npe/include/IxOsalOs.h
@@ -0,0 +1,30 @@
+#ifndef IxOsalOs_H
+#define IxOsalOs_H
+
+#ifndef IX_OSAL_CACHED
+#error "Uncached memory not supported in linux environment"
+#endif
+
+static inline unsigned long __v2p(unsigned long v)
+{
+ if (v < 0x40000000)
+ return (v & 0xfffffff);
+ else
+ return v;
+}
+
+#define IX_OSAL_OS_MMU_VIRT_TO_PHYS(addr) __v2p((u32)addr)
+#define IX_OSAL_OS_MMU_PHYS_TO_VIRT(addr) (addr)
+
+/*
+ * Data cache not enabled (hopefully)
+ */
+#define IX_OSAL_OS_CACHE_INVALIDATE(addr, size)
+#define IX_OSAL_OS_CACHE_FLUSH(addr, size)
+#define HAL_DCACHE_INVALIDATE(addr, size)
+#define HAL_DCACHE_FLUSH(addr, size)
+
+#define __ixp42X /* sr: U-Boot needs this define */
+
+#endif /* IxOsalOs_H */
+