* Code cleanup:

  - remove trailing white space, trailing empty lines, C++ comments, etc.
  - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)

* Patches by Kenneth Johansson, 25 Jun 2003:
  - major rework of command structure
    (work done mostly by Michal Cendrowski and Joakim Kristiansen)

11 files changed, 530 insertions, 539 deletions

diff --git a/cpu/i386/Makefile b/cpu/i386/Makefile
index 7067a06..c44412a 100644
--- a/cpu/i386/Makefile
+++ b/cpu/i386/Makefile
@@ -25,10 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= lib$(CPU).a
 
-START	= start.o start16.o reset.o 
-COBJS	= serial.o interrupts.o cpu.o timer.o sc520.o 
+START	= start.o start16.o reset.o
+COBJS	= serial.o interrupts.o cpu.o timer.o sc520.o
 AOBJS	= sc520_asm.o
-	
+
 all:	.depend $(START) $(LIB)
 
 $(LIB):	$(COBJS) $(AOBJS)
diff --git a/cpu/i386/config.mk b/cpu/i386/config.mk
index c7cf151..16a160d 100644
--- a/cpu/i386/config.mk
+++ b/cpu/i386/config.mk
@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += 
+PLATFORM_RELFLAGS +=
 
 PLATFORM_CPPFLAGS += -march=i386 -Werror
diff --git a/cpu/i386/cpu.c b/cpu/i386/cpu.c
index 3c67c12..f24e4ba 100644
--- a/cpu/i386/cpu.c
+++ b/cpu/i386/cpu.c
@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2002
  * Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
- * 
+ *
  * (C) Copyright 2002
  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Marius Groeger <mgroeger@sysgo.de>
@@ -40,11 +40,11 @@ int cpu_init(void)
 {
 	/* initialize FPU, reset EM, set MP and NE */
 	asm ("fninit\n" \
-             "movl %cr0, %eax\n" \
-             "andl $~0x4, %eax\n" \
-             "orl  $0x22, %eax\n" \
-             "movl %eax, %cr0\n" );
-	
+	     "movl %cr0, %eax\n" \
+	     "andl $~0x4, %eax\n" \
+	     "orl  $0x22, %eax\n" \
+	     "movl %eax, %cr0\n" );
+
 	return 0;
 }
 
@@ -66,4 +66,3 @@ void  flush_cache (unsigned long dummy1, unsigned long dummy2)
 	asm("wbinvd\n");
 	return;
 }
-
diff --git a/cpu/i386/interrupts.c b/cpu/i386/interrupts.c
index 614d408..84825ae 100644
--- a/cpu/i386/interrupts.c
+++ b/cpu/i386/interrupts.c
@@ -29,7 +29,6 @@
 #include <asm/ibmpc.h>
 
 
-
 struct idt_entry {
 	u16	base_low;
 	u16	selector;
@@ -44,7 +43,7 @@ struct idt_entry idt[256];
 
 #define MAX_IRQ 16
 
-typedef struct irq_handler { 
+typedef struct irq_handler {
 	struct irq_handler *next;
 	interrupt_handler_t* isr_func;
 	void *isr_data;
@@ -60,27 +59,26 @@ typedef struct {
 static irq_desc_t irq_table[MAX_IRQ];
 
 
-
 asm(".globl syscall_entry\n" \
-        "syscall_entry:\n" \
-        "popl   %ebx\n"        /* throw away the return address, flags  */ \
-        "popl   %ebx\n"        /* and segment that the INT instruction pushed */ \
-        "popl   %ebx\n"        /* on to the stack */ \
-        "movl   %eax, %ecx\n"  /* load the syscall nr argument*/ \
-        "movl   syscall_tbl, %eax\n" /* load start of syscall table */ \
-        "cmpl   $(11-1), %ecx\n"  /* FixMe: find a way to use NR_SYSCALLS macro here */ \
-        "ja     bad_syscall\n" \
-        "movl   (%eax, %ecx, 4), %eax\n" /* load the handler of the syscall*/ \
-        "test   %eax, %eax\n" /* test for null */ \
-        "je     bad_syscall\n" \
-        "popl   %ecx\n" \
-        "popl   %ebx\n" \
-        "sti    \n" \
-        "jmp    *%eax\n" \
+	"syscall_entry:\n" \
+	"popl   %ebx\n"        /* throw away the return address, flags  */ \
+	"popl   %ebx\n"        /* and segment that the INT instruction pushed */ \
+	"popl   %ebx\n"        /* on to the stack */ \
+	"movl   %eax, %ecx\n"  /* load the syscall nr argument*/ \
+	"movl   syscall_tbl, %eax\n" /* load start of syscall table */ \
+	"cmpl   $(11-1), %ecx\n"  /* FixMe: find a way to use NR_SYSCALLS macro here */ \
+	"ja     bad_syscall\n" \
+	"movl   (%eax, %ecx, 4), %eax\n" /* load the handler of the syscall*/ \
+	"test   %eax, %eax\n" /* test for null */ \
+	"je     bad_syscall\n" \
+	"popl   %ecx\n" \
+	"popl   %ebx\n" \
+	"sti    \n" \
+	"jmp    *%eax\n" \
 "bad_syscall: movl $0xffffffff, %eax\n" \
-        "popl   %ecx\n" \
-        "popl   %ebx\n" \
-        "ret");
+	"popl   %ecx\n" \
+	"popl   %ebx\n" \
+	"ret");
 
 void __attribute__ ((regparm(0))) syscall_entry(void);
 
@@ -104,7 +102,7 @@ char exception_stack[4096];
 		    "pusha \n" \
 		    "pushl $"#x"\n" \
 		    "pushl $irq_return\n" \
-                    "jmp   do_irq\n"); \
+		    "jmp   do_irq\n"); \
 	void __attribute__ ((regparm(0))) irq_##x(void)
 
 #define DECLARE_EXCEPTION(x, f) \
@@ -173,20 +171,20 @@ DECLARE_INTERRUPT(12);
 DECLARE_INTERRUPT(13);
 DECLARE_INTERRUPT(14);
 DECLARE_INTERRUPT(15);
-  
-void __attribute__ ((regparm(0))) default_isr(void); 
+
+void __attribute__ ((regparm(0))) default_isr(void);
 asm ("default_isr: iret\n");
 
-void disable_irq(int irq) 
+void disable_irq(int irq)
 {
 	if (irq >= MAX_IRQ) {
 		return;
 	}
 	irq_table[irq].status |= IRQ_DISABLED;
-	
+
 }
 
-void enable_irq(int irq) 
+void enable_irq(int irq)
 {
 	if (irq >= MAX_IRQ) {
 		return;
@@ -198,7 +196,7 @@ void enable_irq(int irq)
 static void unmask_irq(int irq)
 {
 	int imr_port;
-	
+
 	if (irq >= MAX_IRQ) {
 		return;
 	}
@@ -207,7 +205,7 @@ static void unmask_irq(int irq)
 	} else {
 		imr_port = MASTER_PIC + IMR;
 	}
-	
+
 	outb(inb(imr_port)&~(1<<(irq&7)), imr_port);
 }
 
@@ -216,7 +214,7 @@ static void unmask_irq(int irq)
 static void mask_irq(int irq)
 {
 	int imr_port;
-	
+
 	if (irq >= MAX_IRQ) {
 		return;
 	}
@@ -225,8 +223,8 @@ static void mask_irq(int irq)
 	} else {
 		imr_port = MASTER_PIC + IMR;
 	}
-	
-	outb(inb(imr_port)|(1<<(irq&7)), imr_port); 
+
+	outb(inb(imr_port)|(1<<(irq&7)), imr_port);
 }
 
 
@@ -238,110 +236,110 @@ static void specific_eoi(int irq)
 	if (irq > 7) {
 		outb(OCW2_SEOI|(irq&7), SLAVE_PIC + OCW2);
 		irq = SEOI_IR2;               /* also do IR2 on master */
-	} 
+	}
 	outb(OCW2_SEOI|irq, MASTER_PIC + OCW2);
 }
 
-void __attribute__ ((regparm(0))) do_irq(int irq) 
+void __attribute__ ((regparm(0))) do_irq(int irq)
 {
-	
+
 	mask_irq(irq);
-	
+
 	if (irq_table[irq].status & IRQ_DISABLED) {
 		unmask_irq(irq);
 		specific_eoi(irq);
 		return;
 	}
-	
-	
+
+
 	if (NULL != irq_table[irq].handler) {
 		irq_handler_t *handler;
-		for (handler = irq_table[irq].handler; 
+		for (handler = irq_table[irq].handler;
 		     NULL!= handler; handler = handler->next) {
 			handler->isr_func(handler->isr_data);
 		}
 	} else {
-		if ((irq & 7) != 7) {				
+		if ((irq & 7) != 7) {
 			printf("Spurious irq %d\n", irq);
 		}
-	}		
+	}
 	unmask_irq(irq);
-	specific_eoi(irq);	
+	specific_eoi(irq);
 }
 
 
-void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) unknown_exception_entry(int cause, int ip, int seg)
 {
 	printf("Unknown Exception %d at %04x:%08x\n", cause, seg, ip);
 }
 
-void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) divide_exception_entry(int cause, int ip, int seg)
 {
 	printf("Divide Error (Division by zero) at %04x:%08x\n", seg, ip);
 	while(1);
 }
 
-void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) debug_exception_entry(int cause, int ip, int seg)
 {
 	printf("Debug Interrupt (Single step) at %04x:%08x\n", seg, ip);
 }
 
-void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) nmi_entry(int cause, int ip, int seg)
 {
 	printf("NMI Interrupt at %04x:%08x\n", seg, ip);
 }
-		
-void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg) 
+
+void __attribute__ ((regparm(0))) invalid_instruction_entry(int cause, int ip, int seg)
 {
 	printf("Invalid Instruction at %04x:%08x\n", seg, ip);
 	while(1);
 }
-				
-void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg) 
+
+void __attribute__ ((regparm(0))) double_fault_entry(int cause, int ip, int seg)
 {
 	printf("Double fault at %04x:%08x\n", seg, ip);
 	while(1);
 }
 
-void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) invalid_tss_exception_entry(int cause, int ip, int seg)
 {
 	printf("Invalid TSS at %04x:%08x\n", seg, ip);
 }
-		
-void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg) 
+
+void __attribute__ ((regparm(0))) seg_fault_entry(int cause, int ip, int seg)
 {
 	printf("Segmentation fault at %04x:%08x\n", seg, ip);
 	while(1);
 }
 
-void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) stack_fault_entry(int cause, int ip, int seg)
 {
 	printf("Stack fault at %04x:%08x\n", seg, ip);
 	while(1);
 }
 
-void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) gpf_entry(int cause, int ip, int seg)
 {
 	printf("General protection fault at %04x:%08x\n", seg, ip);
 }
 
-void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) page_fault_entry(int cause, int ip, int seg)
 {
 	printf("Page fault at %04x:%08x\n", seg, ip);
 	while(1);
 }
 
-void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) fp_exception_entry(int cause, int ip, int seg)
 {
 	printf("Floating point exception at %04x:%08x\n", seg, ip);
 }
 
-void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg) 
+void __attribute__ ((regparm(0))) alignment_check_entry(int cause, int ip, int seg)
 {
 	printf("Alignment check at %04x:%08x\n", seg, ip);
 }
-       
-void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg) 
+
+void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg)
 {
 	printf("Machine check exception at %04x:%08x\n", seg, ip);
 }
@@ -350,31 +348,31 @@ void __attribute__ ((regparm(0))) machine_check_entry(int cause, int ip, int seg
 void irq_install_handler(int ino, interrupt_handler_t *func, void *pdata)
 {
 	int status;
-	
+
 	if (ino>MAX_IRQ) {
 		return;
 	}
-		
+
 	if (NULL != irq_table[ino].handler) {
 		return;
 	}
-	
+
 	status = disable_interrupts();
 	irq_table[ino].handler = malloc(sizeof(irq_handler_t));
 	if (NULL == irq_table[ino].handler) {
 		return;
 	}
-	
+
 	memset(irq_table[ino].handler, 0, sizeof(irq_handler_t));
-	
+
 	irq_table[ino].handler->isr_func = func;
 	irq_table[ino].handler->isr_data = pdata;
 	if (status) {
 		enable_interrupts();
 	}
-	
+
 	unmask_irq(ino);
-	
+
 	return;
 }
 
@@ -384,7 +382,7 @@ void irq_free_handler(int ino)
 	if (ino>MAX_IRQ) {
 		return;
 	}
-	
+
 	status = disable_interrupts();
 	mask_irq(ino);
 	if (NULL == irq_table[ino].handler) {
@@ -406,33 +404,33 @@ asm ("idt_ptr:\n"
 
 static void set_vector(int intnum, void *routine)
 {
-	idt[intnum].base_high = (u16)((u32)(routine)>>16);	
-	idt[intnum].base_low = (u16)((u32)(routine)&0xffff);	
+	idt[intnum].base_high = (u16)((u32)(routine)>>16);
+	idt[intnum].base_low = (u16)((u32)(routine)&0xffff);
 }
 
 
 int interrupt_init(void)
 {
 	int i;
-	
+
 	/* Just in case... */
 	disable_interrupts();
-		
+
 	/* Initialize the IDT and stuff */
-	
-	
+
+
 	memset(irq_table, 0, sizeof(irq_table));
 
 	/* Setup the IDT */
-	for (i=0;i<256;i++) {		
+	for (i=0;i<256;i++) {
 		idt[i].access = 0x8e;
-		idt[i].res = 0;	
-		idt[i].selector = 0x10;	
+		idt[i].res = 0;
+		idt[i].selector = 0x10;
 		set_vector(i, default_isr);
-	}	
-	
+	}
+
 	asm ("cs lidt idt_ptr\n");
-	
+
 	/* Setup exceptions */
 	set_vector(0x00, exp_0);
 	set_vector(0x01, exp_1);
@@ -487,39 +485,39 @@ int interrupt_init(void)
 	/* vectors 0x30-0x3f are reserved for irq 16-31 */
 	set_vector(0x40, syscall_entry);
 
-	
+
 	/* Mask all interrupts */
 	outb(0xff, MASTER_PIC + IMR);
 	outb(0xff, SLAVE_PIC + IMR);
-	
+
 	/* Master PIC */
-	outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);	
+	outb(ICW1_SEL|ICW1_EICW4, MASTER_PIC + ICW1);
 	outb(0x20, MASTER_PIC + ICW2);          /* Place master PIC interrupts at INT20 */
-	outb(IR2, MASTER_PIC + ICW3);		/* ICW3, One slevc PIC is present */	
+	outb(IR2, MASTER_PIC + ICW3);		/* ICW3, One slevc PIC is present */
 	outb(ICW4_PM, MASTER_PIC + ICW4);
-	
+
 	for (i=0;i<8;i++) {
 		outb(OCW2_SEOI|i, MASTER_PIC + OCW2);
 	}
-	
+
 	/* Slave PIC */
-	outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);	
+	outb(ICW1_SEL|ICW1_EICW4, SLAVE_PIC + ICW1);
 	outb(0x28, SLAVE_PIC + ICW2);	        /* Place slave PIC interrupts at INT28 */
 	outb(0x02, SLAVE_PIC + ICW3);		/* Slave ID */
-	outb(ICW4_PM, SLAVE_PIC + ICW4);        
-	
+	outb(ICW4_PM, SLAVE_PIC + ICW4);
+
 	for (i=0;i<8;i++) {
 		outb(OCW2_SEOI|i, SLAVE_PIC + OCW2);
 	}
-	
-	
+
+
 	/* enable cascade interrerupt */
 	outb(0xfb, MASTER_PIC + IMR);
 	outb(0xff, SLAVE_PIC + IMR);
-	
+
 	/* It is now safe to enable interrupts */
-	enable_interrupts(); 
-	
+	enable_interrupts();
+
 	return 0;
 }
 
@@ -531,9 +529,9 @@ void enable_interrupts(void)
 int disable_interrupts(void)
 {
 	long flags;
-	
+
 	asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
-	
+
 	return (flags&0x200); /* IE flags is bit 9 */
 }
 
@@ -541,9 +539,9 @@ int disable_interrupts(void)
 #ifdef CFG_RESET_GENERIC
 
 void __attribute__ ((regparm(0))) generate_gpf(void);
-asm(".globl generate_gpf\n" 
-    "generate_gpf:\n" 
-    "ljmp   $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not 
+asm(".globl generate_gpf\n"
+    "generate_gpf:\n"
+    "ljmp   $0x70, $0x47114711\n"); /* segment 0x70 is an arbitrary segment which does not
 				    * exist */
 void reset_cpu(ulong addr)
 {
diff --git a/cpu/i386/reset.S b/cpu/i386/reset.S
index 57e32a8..07a7384 100644
--- a/cpu/i386/reset.S
+++ b/cpu/i386/reset.S
@@ -1,5 +1,5 @@
 /*
- *  U-boot - i386 Startup Code 
+ *  U-boot - i386 Startup Code
  *
  *  Copyright (c) 2002	Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
  *
@@ -28,11 +28,10 @@
 
 .section .reset, "ax"
 .code16
-reset_vector: 
-        cli
-        cld
-        jmp start16 
+reset_vector:
+	cli
+	cld
+	jmp start16
 
 	.org 0xf
 	nop
-	
diff --git a/cpu/i386/sc520.c b/cpu/i386/sc520.c
index 500089a..689e775 100644
--- a/cpu/i386/sc520.c
+++ b/cpu/i386/sc520.c
@@ -36,26 +36,26 @@
 #include <asm/pci.h>
 #include <asm/ic/sc520.h>
 
-/* 
- * utility functions for boards based on the AMD sc520 
- * 
+/*
+ * utility functions for boards based on the AMD sc520
+ *
  * void write_mmcr_byte(u16 mmcr, u8 data)
  * void write_mmcr_word(u16 mmcr, u16 data)
  * void write_mmcr_long(u16 mmcr, u32 data)
- * 
+ *
  * u8   read_mmcr_byte(u16 mmcr)
  * u16  read_mmcr_word(u16 mmcr)
  * u32  read_mmcr_long(u16 mmcr)
- * 
+ *
  * void init_sc520(void)
  * unsigned long init_sc520_dram(void)
  * void pci_sc520_init(struct pci_controller *hose)
- * 
+ *
  * void reset_timer(void)
  * ulong get_timer(ulong base)
  * void set_timer(ulong t)
  * void udelay(unsigned long usec)
- * 
+ *
  */
 
 static u32 mmcr_base= 0xfffef000;
@@ -67,7 +67,7 @@ void write_mmcr_byte(u16 mmcr, u8 data)
 
 void write_mmcr_word(u16 mmcr, u16 data)
 {
-	writew(data, mmcr+mmcr_base);	
+	writew(data, mmcr+mmcr_base);
 }
 
 void write_mmcr_long(u16 mmcr, u32 data)
@@ -82,7 +82,7 @@ u8 read_mmcr_byte(u16 mmcr)
 
 u16 read_mmcr_word(u16 mmcr)
 {
-	return readw(mmcr+mmcr_base);	
+	return readw(mmcr+mmcr_base);
 }
 
 u32 read_mmcr_long(u16 mmcr)
@@ -94,19 +94,19 @@ u32 read_mmcr_long(u16 mmcr)
 void init_sc520(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	
+
 	/* Set the UARTxCTL register at it's slower,
-	 * baud clock giving us a 1.8432 MHz reference 
+	 * baud clock giving us a 1.8432 MHz reference
 	 */
 	write_mmcr_byte(SC520_UART1CTL, 7);
 	write_mmcr_byte(SC520_UART2CTL, 7);
-	
+
 	/* first set the timer pin mapping */
 	write_mmcr_byte(SC520_CLKSEL, 0x72);	/* no clock frequency selected, use 1.1892MHz */
-	
+
 	/* enable PCI bus arbitrer */
 	write_mmcr_byte(SC520_SYSARBCTL,0x02);  /* enable concurrent mode */
-	
+
 	write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
 	write_mmcr_word(SC520_HBCTL,0x04);      /* enable posted-writes */
 
@@ -120,10 +120,10 @@ void init_sc520(void)
 		printf("## CPU Speed set to 100MHz\n");
 		gd->cpu_clk = 100000000;
 	}
-	
+
 
 	/* wait at least one millisecond */
-        asm("movl	$0x2000,%%ecx\n"
+	asm("movl	$0x2000,%%ecx\n"
 	    "wait_loop:	pushl %%ecx\n"
 	    "popl	%%ecx\n"
 	    "loop wait_loop\n": : : "ecx");
@@ -141,19 +141,19 @@ unsigned long init_sc520_dram(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	bd_t *bd = gd->bd;
-	
+
 	u32 dram_present=0;
 	u32 dram_ctrl;
 
 	int val;
-	
-	int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;	
-	int refresh_rate        = CFG_SDRAM_REFRESH_RATE;	
+
+	int cas_precharge_delay = CFG_SDRAM_PRECHARGE_DELAY;
+	int refresh_rate        = CFG_SDRAM_REFRESH_RATE;
 	int ras_cas_delay       = CFG_SDRAM_RAS_CAS_DELAY;
-	
+
 	/* set SDRAM speed here */
-	
-	refresh_rate/=78;	
+
+	refresh_rate/=78;
 	if (refresh_rate<=1) {
 		val = 0;  /* 7.8us */
 	} else if (refresh_rate==2) {
@@ -164,22 +164,22 @@ unsigned long init_sc520_dram(void)
 		val = 3;  /* 62.4us */
 	}
 	write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
-	
+
 	val = read_mmcr_byte(SC520_DRCTMCTL);
 	val &= 0xf0;
-	
-	if (cas_precharge_delay==3) {		
+
+	if (cas_precharge_delay==3) {
 		val |= 0x04;   /* 3T */
-	} else if (cas_precharge_delay==4) {		
+	} else if (cas_precharge_delay==4) {
 		val |= 0x08;   /* 4T */
-	} else if (cas_precharge_delay>4) {		
+	} else if (cas_precharge_delay>4) {
 		val |= 0x0c;
-	} 
-	
+	}
+
 	if (ras_cas_delay > 3) {
-		val |= 2; 
+		val |= 2;
 	} else {
-		val |= 1; 
+		val |= 1;
 	}
 	write_mmcr_byte(SC520_DRCTMCTL, val);
 
@@ -187,37 +187,37 @@ unsigned long init_sc520_dram(void)
 	/* We read-back the configuration of the dram
 	 * controller that the assembly code wrote */
 	dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
-	
+
 
 	bd->bi_dram[0].start = 0;
 	if (dram_ctrl & 0x80) {
 		/* bank 0 enabled */
 		dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
-		bd->bi_dram[0].size = bd->bi_dram[1].start; 
+		bd->bi_dram[0].size = bd->bi_dram[1].start;
 
 	} else {
 		bd->bi_dram[0].size = 0;
 		bd->bi_dram[1].start = bd->bi_dram[0].start;
 	}
-	
+
 	if (dram_ctrl & 0x8000) {
 		/* bank 1 enabled */
 		dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
-		bd->bi_dram[1].size = bd->bi_dram[2].start -  bd->bi_dram[1].start; 
+		bd->bi_dram[1].size = bd->bi_dram[2].start -  bd->bi_dram[1].start;
 	} else {
 		bd->bi_dram[1].size = 0;
 		bd->bi_dram[2].start = bd->bi_dram[1].start;
 	}
-	
+
 	if (dram_ctrl & 0x800000) {
 		/* bank 2 enabled */
 		dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
-		bd->bi_dram[2].size = bd->bi_dram[3].start -  bd->bi_dram[2].start; 
+		bd->bi_dram[2].size = bd->bi_dram[3].start -  bd->bi_dram[2].start;
 	} else {
 		bd->bi_dram[2].size = 0;
 		bd->bi_dram[3].start = bd->bi_dram[2].start;
-	} 
-	
+	}
+
 	if (dram_ctrl & 0x80000000) {
 		/* bank 3 enabled */
 		dram_present  = (dram_ctrl & 0x7f000000) >> 2;
@@ -226,12 +226,12 @@ unsigned long init_sc520_dram(void)
 		bd->bi_dram[3].size = 0;
 	}
 
-	
-#if 0	
+
+#if 0
 	printf("Configured %d bytes of dram\n", dram_present);
-#endif	
+#endif
 	gd->ram_size = dram_present;
-	
+
 	return dram_present;
 }
 
@@ -265,19 +265,19 @@ static struct {
 
 
 /* The interrupt used for PCI INTA-INTD  */
-int sc520_pci_ints[15] = { 
+int sc520_pci_ints[15] = {
 	-1, -1, -1, -1, -1, -1, -1, -1,
 		-1, -1, -1, -1, -1, -1, -1
 };
 
 /* utility function to configure a pci interrupt */
-int pci_sc520_set_irq(int pci_pin, int irq) 
+int pci_sc520_set_irq(int pci_pin, int irq)
 {
 	int i;
-	
+
 # if 0
 	printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
-#endif	
+#endif
 	if (irq < 0 || irq > 15) {
 		return -1; /* illegal irq */
 	}
@@ -286,7 +286,7 @@ int pci_sc520_set_irq(int pci_pin, int irq)
 		return -1; /* illegal pci int pin */
 	}
 
-	/* first disable any non-pci interrupt source that use 
+	/* first disable any non-pci interrupt source that use
 	 * this level */
 	for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
 		if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
@@ -296,31 +296,31 @@ int pci_sc520_set_irq(int pci_pin, int irq)
 			write_mmcr_byte(i, SC520_IRQ_DISABLED);
 		}
 	}
-	
+
 	/* Set the trigger to level */
-	write_mmcr_byte(sc520_irq[irq].level_reg, 
+	write_mmcr_byte(sc520_irq[irq].level_reg,
 			read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
-	
-	
+
+
 	if (pci_pin < 4) {
 		/* PCI INTA-INTD */
 		/* route the interrupt */
 		write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
-		
-		
+
+
 	} else {
 		/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
 		write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
-		
+
 		/* also set the polarity in this case */
-		write_mmcr_word(SC520_INTPINPOL, 
+		write_mmcr_word(SC520_INTPINPOL,
 				read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
-		
+
 	}
-	
-	/* register the pin */		
+
+	/* register the pin */
 	sc520_pci_ints[pci_pin] = irq;
-	
+
 
 	return 0; /* OK */
 }
@@ -331,35 +331,35 @@ void pci_sc520_init(struct pci_controller *hose)
 	hose->last_busno = 0xff;
 
 	/* System memory space */
-	pci_set_region(hose->regions + 0, 
+	pci_set_region(hose->regions + 0,
 		       SC520_PCI_MEMORY_BUS,
 		       SC520_PCI_MEMORY_PHYS,
 		       SC520_PCI_MEMORY_SIZE,
 		       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 	/* PCI memory space */
-	pci_set_region(hose->regions + 1, 
+	pci_set_region(hose->regions + 1,
 		       SC520_PCI_MEM_BUS,
 		       SC520_PCI_MEM_PHYS,
 		       SC520_PCI_MEM_SIZE,
 		       PCI_REGION_MEM);
 
 	/* ISA/PCI memory space */
-	pci_set_region(hose->regions + 2, 
+	pci_set_region(hose->regions + 2,
 		       SC520_ISA_MEM_BUS,
 		       SC520_ISA_MEM_PHYS,
 		       SC520_ISA_MEM_SIZE,
 		       PCI_REGION_MEM);
 
 	/* PCI I/O space */
-	pci_set_region(hose->regions + 3, 
+	pci_set_region(hose->regions + 3,
 		       SC520_PCI_IO_BUS,
 		       SC520_PCI_IO_PHYS,
 		       SC520_PCI_IO_SIZE,
 		       PCI_REGION_IO);
 
 	/* ISA/PCI I/O space */
-	pci_set_region(hose->regions + 4, 
+	pci_set_region(hose->regions + 4,
 		       SC520_ISA_IO_BUS,
 		       SC520_ISA_IO_PHYS,
 		       SC520_ISA_IO_SIZE,
@@ -374,15 +374,14 @@ void pci_sc520_init(struct pci_controller *hose)
 	pci_register_hose(hose);
 
 	hose->last_busno = pci_hose_scan(hose);
-	
+
 	/* enable target memory acceses on host brige */
-	pci_write_config_word(0, PCI_COMMAND, 
+	pci_write_config_word(0, PCI_COMMAND,
 			      PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 
 }
 
 
-
 #endif
 
 #ifdef CFG_TIMER_SC520
@@ -392,7 +391,7 @@ void reset_timer(void)
 {
 	write_mmcr_word(SC520_GPTMR0CNT, 0);
 	write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
-	
+
 }
 
 ulong get_timer(ulong base)
@@ -414,19 +413,19 @@ void udelay(unsigned long usec)
 {
 	int m=0;
 	long u;
-	
+
 	read_mmcr_word(SC520_SWTMRMILLI);
 	read_mmcr_word(SC520_SWTMRMICRO);
-	     
+
 #if 0
 	/* do not enable this line, udelay is used in the serial driver -> recursion */
 	printf("udelay: %ld m.u %d.%d  tm.tu %d.%d\n", usec, m, u, tm, tu);
-#endif	
+#endif
 	while (1) {
-		
+
 		m += read_mmcr_word(SC520_SWTMRMILLI);
 		u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
-		
+
 		if (usec <= u) {
 			break;
 		}
@@ -440,13 +439,13 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
 	u8 temp=0;
 
 	if (freq >= 8192) {
-		temp |= CTL_CLK_SEL_4; 
+		temp |= CTL_CLK_SEL_4;
 	} else if (freq >= 4096) {
-		temp |= CTL_CLK_SEL_8;        
+		temp |= CTL_CLK_SEL_8;
 	} else if (freq >= 2048) {
-		temp |= CTL_CLK_SEL_16;  
+		temp |= CTL_CLK_SEL_16;
 	} else if (freq >= 1024) {
-		temp |= CTL_CLK_SEL_32;  
+		temp |= CTL_CLK_SEL_32;
 	} else if (freq >= 512) {
 		temp |= CTL_CLK_SEL_64;
 	} else if (freq >= 256) {
@@ -456,47 +455,47 @@ int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
 	} else {
 		temp |= CTL_CLK_SEL_512;
 	}
-	
+
 	if (!lsb_first) {
 		temp |= MSBF_ENB;
 	}
-		
+
 	if (inv_clock) {
 		temp |= CLK_INV_ENB;
 	}
-	
+
 	if (inv_phase) {
 		temp |= PHS_INV_ENB;
 	}
-		
+
 	write_mmcr_byte(SC520_SSICTL, temp);
-	
+
 	return 0;
 }
 
-u8 ssi_txrx_byte(u8 data) 
+u8 ssi_txrx_byte(u8 data)
 {
 	write_mmcr_byte(SC520_SSIXMIT, data);
 	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
 	write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
 	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	return read_mmcr_byte(SC520_SSIRCV);	
-}      
+	return read_mmcr_byte(SC520_SSIRCV);
+}
 
 
-void ssi_tx_byte(u8 data) 
+void ssi_tx_byte(u8 data)
 {
 	write_mmcr_byte(SC520_SSIXMIT, data);
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY); 
+	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
 	write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
 }
 
-u8 ssi_rx_byte(void) 
+u8 ssi_rx_byte(void)
 {
 	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
 	write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
 	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
 	return read_mmcr_byte(SC520_SSIRCV);
-} 
+}
 
 #endif /* CONFIG_SC520 */
diff --git a/cpu/i386/sc520_asm.S b/cpu/i386/sc520_asm.S
index 7a957c7..80464fa 100644
--- a/cpu/i386/sc520_asm.S
+++ b/cpu/i386/sc520_asm.S
@@ -22,21 +22,21 @@
  */
 
 /* This file is largely based on code obtned from AMD. AMD's original
- * copyright is included below 
+ * copyright is included below
  */
 
 /*
  *  =============================================================================
- *                                                                              
- *   Copyright 1999 Advanced Micro Devices, Inc.                                
- *                                                                              
- *  This software is the property of Advanced Micro Devices, Inc  (AMD)  which 
- *  specifically grants the user the right to modify, use and distribute this 
- *  software provided this COPYRIGHT NOTICE is not removed or altered.  All 
- *  other rights are reserved by AMD.                                                       
- *                                                                             
- *  THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY 
- *  OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF 
+ *
+ *   Copyright 1999 Advanced Micro Devices, Inc.
+ *
+ *  This software is the property of Advanced Micro Devices, Inc  (AMD)  which
+ *  specifically grants the user the right to modify, use and distribute this
+ *  software provided this COPYRIGHT NOTICE is not removed or altered.  All
+ *  other rights are reserved by AMD.
+ *
+ *  THE MATERIALS ARE PROVIDED "AS IS" WITHOUT ANY EXPRESS OR IMPLIED WARRANTY
+ *  OF ANY KIND INCLUDING WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT OF
  *  THIRD-PARTY INTELLECTUAL PROPERTY, OR FITNESS FOR ANY PARTICULAR PURPOSE.
  *  IN NO EVENT SHALL AMD OR ITS SUPPLIERS BE LIABLE FOR ANY DAMAGES WHATSOEVER
  *  (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS
@@ -45,19 +45,19 @@
  *  SUCH DAMAGES.  BECAUSE SOME JURSIDICTIONS PROHIBIT THE EXCLUSION OR
  *  LIMITATION OF LIABILITY FOR CONSEQUENTIAL OR INCIDENTAL DAMAGES, THE ABOVE
  *  LIMITATION MAY NOT APPLY TO YOU.
- * 
+ *
  *  AMD does not assume any responsibility for any errors that may appear in
  *  the Materials nor any responsibility to support or update the Materials.
  *  AMD retains the right to make changes to its test specifications at any
  *  time, without notice.
- * 
- *  So that all may benefit from your experience, please report  any  problems 
- *  or suggestions about this software back to AMD.  Please include your name, 
- *  company,  telephone number,  AMD product requiring support and question or 
- *  problem encountered.                                                       
- *                                                                             
- *  Advanced Micro Devices, Inc.         Worldwide support and contact           
- *  Embedded Processor Division            information available at:               
+ *
+ *  So that all may benefit from your experience, please report  any  problems
+ *  or suggestions about this software back to AMD.  Please include your name,
+ *  company,  telephone number,  AMD product requiring support and question or
+ *  problem encountered.
+ *
+ *  Advanced Micro Devices, Inc.         Worldwide support and contact
+ *  Embedded Processor Division            information available at:
  *  Systems Engineering                       epd.support@amd.com
  *  5204 E. Ben White Blvd.                          -or-
  *  Austin, TX 78741                http://www.amd.com/html/support/techsup.html
@@ -66,7 +66,7 @@
 
 
 /*******************************************************************************
- *	 AUTHOR      : Buddy Fey - Original. 
+ *	 AUTHOR      : Buddy Fey - Original.
  *******************************************************************************
  */
 
@@ -140,368 +140,368 @@
   * initialize dram controller registers
   */
 .globl mem_init
-mem_init: 
-        xorw    %ax,%ax
-        movl    $DBCTL, %edi             
+mem_init:
+	xorw    %ax,%ax
+	movl    $DBCTL, %edi
 	movb     %al, (%edi)             /* disable write buffer */
 
-        movl    $ECCCTL, %edi            
+	movl    $ECCCTL, %edi
 	movb     %al, (%edi)             /* disable ECC */
 
-        movl    $DRCTMCTL, %edi           
-        movb    $0x1E,%al                /* Set SDRAM timing for slowest */
+	movl    $DRCTMCTL, %edi
+	movb    $0x1E,%al                /* Set SDRAM timing for slowest */
 	movb     %al, (%edi)
 
  /*
   * setup loop to do 4 external banks starting with bank 3
   */
-        movl    $0xff000000,%eax         /* enable last bank and setup */
-        movl    $DRCBENDADR, %edi        /* ending address register */
+	movl    $0xff000000,%eax         /* enable last bank and setup */
+	movl    $DRCBENDADR, %edi        /* ending address register */
 	movl     %eax, (%edi)
 
-        movl    $DRCCFG, %edi            /* setup */
-        movw    $0xbbbb,%ax              /* dram config register for  */
+	movl    $DRCCFG, %edi            /* setup */
+	movw    $0xbbbb,%ax              /* dram config register for  */
 	movw    %ax, (%edi)
 
  /*
   * issue a NOP to all DRAMs
   */
-        movl    $DRCCTL, %edi            /* setup DRAM control register with */
-        movb    $0x1,%al                 /* Disable refresh,disable write buffer */ 
+	movl    $DRCCTL, %edi            /* setup DRAM control register with */
+	movb    $0x1,%al                 /* Disable refresh,disable write buffer */
 	movb     %al, (%edi)
-        movl    $CACHELINESZ, %esi       /* just a dummy address to write for */ 
+	movl    $CACHELINESZ, %esi       /* just a dummy address to write for */
 	movw     %ax, (%esi)
  /*
   * delay for 100 usec? 200?
   * ******this is a cludge for now *************
   */
-        movw    $100,%cx
-sizdelay: 
-        loop    sizdelay                 /* we need 100 usec here */
+	movw    $100,%cx
+sizdelay:
+	loop    sizdelay                 /* we need 100 usec here */
  /***********************************************/
 
  /*
   * issue all banks precharge
   */
-        movb    $0x2,%al                 /* All banks precharge */
+	movb    $0x2,%al                 /* All banks precharge */
 	movb     %al, (%edi)
 	movw     %ax, (%esi)
 
  /*
-  * issue 2 auto refreshes to all banks 
+  * issue 2 auto refreshes to all banks
   */
-        movb    $0x4,%al                 /* Auto refresh cmd */
+	movb    $0x4,%al                 /* Auto refresh cmd */
 	movb     %al, (%edi)
-        movw    $2,%cx
-refresh1: 
+	movw    $2,%cx
+refresh1:
 	movw     %ax, (%esi)
-        loop    refresh1
+	loop    refresh1
 
  /*
   * issue LOAD MODE REGISTER command
   */
-        movb    $0x3,%al                 /* Load mode register cmd */
+	movb    $0x3,%al                 /* Load mode register cmd */
 	movb     %al, (%edi)
 	movw     %ax, (%esi)
 
  /*
-  * issue 8 more auto refreshes to all banks 
-  */ 
-        movb    $0x4,%al                 /* Auto refresh cmd */
+  * issue 8 more auto refreshes to all banks
+  */
+	movb    $0x4,%al                 /* Auto refresh cmd */
 	movb     %al, (%edi)
-        movw    $8,%cx
-refresh2: 
+	movw    $8,%cx
+refresh2:
 	movw     %ax, (%esi)
-        loop    refresh2
+	loop    refresh2
 
  /*
-  * set control register to NORMAL mode 
+  * set control register to NORMAL mode
   */
-        movb    $0x0,%al                 /* Normal mode value */
+	movb    $0x0,%al                 /* Normal mode value */
 	movb     %al, (%edi)
 
  /*
   * size dram starting with external bank 3 moving to external bank 0
   */
-        movl    $0x3,%ecx                /* start with external bank 3 */
+	movl    $0x3,%ecx                /* start with external bank 3 */
 
-nextbank: 
+nextbank:
 
  /*
   * write col 11 wrap adr
   */
-        movl    $COL11_ADR, %esi         /* set address to max col (11) wrap addr */
-        movl    $COL11_DATA, %eax        /* pattern for max supported columns(11) */
+	movl    $COL11_ADR, %esi         /* set address to max col (11) wrap addr */
+	movl    $COL11_DATA, %eax        /* pattern for max supported columns(11) */
 	movl    %eax, (%esi)             /* write max col pattern at max col adr */
 	movl    (%esi), %ebx             /* optional read */
-        cmpl    %ebx,%eax                /* to verify write */
-        jnz     bad_ram                  /* this ram is bad */
+	cmpl    %ebx,%eax                /* to verify write */
+	jnz     bad_ram                  /* this ram is bad */
  /*
   * write col 10 wrap adr
   */
 
-        movl    $COL10_ADR, %esi         /* set address to 10 col wrap address */
-        movl    $COL10_DATA, %eax        /* pattern for 10 col wrap */
+	movl    $COL10_ADR, %esi         /* set address to 10 col wrap address */
+	movl    $COL10_DATA, %eax        /* pattern for 10 col wrap */
 	movl    %eax, (%esi)             /* write 10 col pattern @ 10 col wrap adr */
 	movl    (%esi), %ebx             /* optional read */
-        cmpl    %ebx,%eax                /* to verify write */
-        jnz     bad_ram                  /* this ram is bad */
+	cmpl    %ebx,%eax                /* to verify write */
+	jnz     bad_ram                  /* this ram is bad */
  /*
   * write col 9 wrap adr
   */
-        movl    $COL09_ADR, %esi         /* set address to 9 col wrap address */
-        movl    $COL09_DATA, %eax        /* pattern for 9 col wrap */
+	movl    $COL09_ADR, %esi         /* set address to 9 col wrap address */
+	movl    $COL09_DATA, %eax        /* pattern for 9 col wrap */
 	movl    %eax, (%esi)             /* write 9 col pattern @ 9 col wrap adr */
 	movl    (%esi), %ebx             /* optional read */
-        cmpl    %ebx,%eax                /* to verify write */
-        jnz     bad_ram                  /* this ram is bad */
+	cmpl    %ebx,%eax                /* to verify write */
+	jnz     bad_ram                  /* this ram is bad */
  /*
   * write col 8 wrap adr
   */
-        movl    $COL08_ADR, %esi         /* set address to min(8) col wrap address */
-        movl    $COL08_DATA, %eax        /* pattern for min (8) col wrap */
+	movl    $COL08_ADR, %esi         /* set address to min(8) col wrap address */
+	movl    $COL08_DATA, %eax        /* pattern for min (8) col wrap */
 	movl    %eax, (%esi)             /* write min col pattern @ min col adr */
 	movl    (%esi), %ebx             /* optional read */
-        cmpl    %ebx,%eax                /* to verify write */
-        jnz     bad_ram                  /* this ram is bad */
+	cmpl    %ebx,%eax                /* to verify write */
+	jnz     bad_ram                  /* this ram is bad */
  /*
   * write row 14 wrap adr
   */
-        movl    $ROW14_ADR, %esi         /* set address to max row (14) wrap addr */
-        movl    $ROW14_DATA, %eax        /* pattern for max supported rows(14) */
+	movl    $ROW14_ADR, %esi         /* set address to max row (14) wrap addr */
+	movl    $ROW14_DATA, %eax        /* pattern for max supported rows(14) */
 	movl    %eax, (%esi)             /* write max row pattern at max row adr */
 	movl    (%esi), %ebx             /* optional read */
-        cmpl    %ebx,%eax                /* to verify write */
-        jnz     bad_ram                  /* this ram is bad */
+	cmpl    %ebx,%eax                /* to verify write */
+	jnz     bad_ram                  /* this ram is bad */
  /*
   * write row 13 wrap adr
   */
-        movl    $ROW13_ADR, %esi         /* set address to 13 row wrap address */
-        movl    $ROW13_DATA, %eax        /* pattern for 13 row wrap */
+	movl    $ROW13_ADR, %esi         /* set address to 13 row wrap address */
+	movl    $ROW13_DATA, %eax        /* pattern for 13 row wrap */
 	movl    %eax, (%esi)             /* write 13 row pattern @ 13 row wrap adr */
 	movl    (%esi), %ebx             /* optional read */
-        cmpl    %ebx,%eax                /* to verify write */
-        jnz     bad_ram                  /* this ram is bad */
+	cmpl    %ebx,%eax                /* to verify write */
+	jnz     bad_ram                  /* this ram is bad */
  /*
   * write row 12 wrap adr
   */
-        movl    $ROW12_ADR, %esi         /* set address to 12 row wrap address */
-        movl    $ROW12_DATA, %eax        /* pattern for 12 row wrap */
+	movl    $ROW12_ADR, %esi         /* set address to 12 row wrap address */
+	movl    $ROW12_DATA, %eax        /* pattern for 12 row wrap */
 	movl    %eax, (%esi)             /* write 12 row pattern @ 12 row wrap adr */
 	movl    (%esi), %ebx             /* optional read */
-        cmpl    %ebx,%eax                /* to verify write */
-        jnz     bad_ram                  /* this ram is bad */
+	cmpl    %ebx,%eax                /* to verify write */
+	jnz     bad_ram                  /* this ram is bad */
  /*
   * write row 11 wrap adr
   */
-        movl    $ROW11_ADR, %edi         /* set address to 11 row wrap address */
-        movl    $ROW11_DATA, %eax        /* pattern for 11 row wrap */
+	movl    $ROW11_ADR, %edi         /* set address to 11 row wrap address */
+	movl    $ROW11_DATA, %eax        /* pattern for 11 row wrap */
 	movl    %eax, (%edi)             /* write 11 row pattern @ 11 row wrap adr */
 	movl    (%edi), %ebx             /* optional read */
-        cmpl    %ebx,%eax                /* to verify write */
-        jnz     bad_ram                  /* this ram is bad */
+	cmpl    %ebx,%eax                /* to verify write */
+	jnz     bad_ram                  /* this ram is bad */
  /*
   * write row 10 wrap adr --- this write is really to determine number of banks
   */
-        movl    $ROW10_ADR, %edi         /* set address to 10 row wrap address */
-        movl    $ROW10_DATA, %eax        /* pattern for 10 row wrap (AA) */
+	movl    $ROW10_ADR, %edi         /* set address to 10 row wrap address */
+	movl    $ROW10_DATA, %eax        /* pattern for 10 row wrap (AA) */
 	movl    %eax, (%edi)             /* write 10 row pattern @ 10 row wrap adr */
 	movl    (%edi), %ebx             /* optional read */
-        cmpl    %ebx,%eax                /* to verify write */
-        jnz     bad_ram                  /* this ram is bad */
+	cmpl    %ebx,%eax                /* to verify write */
+	jnz     bad_ram                  /* this ram is bad */
  /*
-  * read data @ row 12 wrap adr to determine  * banks, 
+  * read data @ row 12 wrap adr to determine  * banks,
   * and read data @ row 14 wrap adr to determine  * rows.
   * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
-  * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4 
+  * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
   * if data @ row 12 wrap == 11 or 12, we have 4 banks,
   */
-        xorw    %di,%di                  /* value for 2 banks in DI */
-	movl    (%esi), %ebx             /* read from 12 row wrap to check banks 
-                                          * (esi is setup from the write to row 12 wrap) */
-        cmpl    %ebx,%eax                /* check for AA pattern  (eax holds the aa pattern) */
-        jz      only2                    /* if pattern == AA, we only have 2 banks */
+	xorw    %di,%di                  /* value for 2 banks in DI */
+	movl    (%esi), %ebx             /* read from 12 row wrap to check banks
+					  * (esi is setup from the write to row 12 wrap) */
+	cmpl    %ebx,%eax                /* check for AA pattern  (eax holds the aa pattern) */
+	jz      only2                    /* if pattern == AA, we only have 2 banks */
 
 	/* 4 banks */
-	
-        movw    $8,%di                   /* value for 4 banks in DI (BNK_CNT bit) */
-        cmpl    $ROW11_DATA, %ebx        /* only other legitimate values are 11 */
-        jz      only2
-        cmpl    $ROW12_DATA, %ebx        /* and 12 */
-        jnz     bad_ram                  /* its bad if not 11 or 12! */
-	
+
+	movw    $8,%di                   /* value for 4 banks in DI (BNK_CNT bit) */
+	cmpl    $ROW11_DATA, %ebx        /* only other legitimate values are 11 */
+	jz      only2
+	cmpl    $ROW12_DATA, %ebx        /* and 12 */
+	jnz     bad_ram                  /* its bad if not 11 or 12! */
+
 	/* fall through */
-only2: 
+only2:
  /*
   * validate row mask
   */
-        movl    $ROW14_ADR, %esi         /* set address back to max row wrap addr */
+	movl    $ROW14_ADR, %esi         /* set address back to max row wrap addr */
 	movl    (%esi), %eax             /* read actual number of rows @ row14 adr */
 
-        cmpl    $ROW11_DATA, %eax        /* row must be greater than 11 pattern */
-        jb      bad_ram
+	cmpl    $ROW11_DATA, %eax        /* row must be greater than 11 pattern */
+	jb      bad_ram
 
-        cmpl    $ROW14_DATA, %eax        /* and row must be less than 14 pattern */
-        ja      bad_ram
+	cmpl    $ROW14_DATA, %eax        /* and row must be less than 14 pattern */
+	ja      bad_ram
 
-        cmpb    %ah,%al                  /* verify all 4 bytes of dword same */
-        jnz     bad_ram
-        movl    %eax,%ebx
-        shrl    $16,%ebx
-        cmpw    %bx,%ax
-        jnz     bad_ram
+	cmpb    %ah,%al                  /* verify all 4 bytes of dword same */
+	jnz     bad_ram
+	movl    %eax,%ebx
+	shrl    $16,%ebx
+	cmpw    %bx,%ax
+	jnz     bad_ram
  /*
   * read col 11 wrap adr for real column data value
   */
-        movl    $COL11_ADR, %esi         /* set address to max col (11) wrap addr */
+	movl    $COL11_ADR, %esi         /* set address to max col (11) wrap addr */
 	movl    (%esi), %eax             /* read real col number at max col adr */
  /*
   * validate column data
   */
-        cmpl    $COL08_DATA, %eax        /* col must be greater than 8 pattern */
-        jb      bad_ram
-
-        cmpl    $COL11_DATA, %eax        /* and row must be less than 11 pattern */
-        ja      bad_ram
-
-        subl    $COL08_DATA, %eax        /* normalize column data to zero */
-        jc      bad_ram
-        cmpb    %ah,%al                  /* verify all 4 bytes of dword equal */
-        jnz     bad_ram
-        movl    %eax,%edx
-        shrl    $16,%edx
-        cmpw    %dx,%ax
-        jnz     bad_ram
+	cmpl    $COL08_DATA, %eax        /* col must be greater than 8 pattern */
+	jb      bad_ram
+
+	cmpl    $COL11_DATA, %eax        /* and row must be less than 11 pattern */
+	ja      bad_ram
+
+	subl    $COL08_DATA, %eax        /* normalize column data to zero */
+	jc      bad_ram
+	cmpb    %ah,%al                  /* verify all 4 bytes of dword equal */
+	jnz     bad_ram
+	movl    %eax,%edx
+	shrl    $16,%edx
+	cmpw    %dx,%ax
+	jnz     bad_ram
  /*
   * merge bank and col data together
   */
-        addw    %di,%dx                  /* merge of bank and col info in dl */
+	addw    %di,%dx                  /* merge of bank and col info in dl */
  /*
   * fix ending addr mask based upon col info
   */
-        movb    $3,%al
-        subb    %dh,%al                  /* dh contains the overflow from the bank/col merge  */
-        movb    %bl,%dh                  /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
-        xchgw   %cx,%ax                  /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
-        shrb    %cl,%dh	                 /*  */
-        incb    %dh                      /* ending addr is 1 greater than real end */
-        xchgw   %cx,%ax                  /* cx is bank number again */
+	movb    $3,%al
+	subb    %dh,%al                  /* dh contains the overflow from the bank/col merge  */
+	movb    %bl,%dh                  /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
+	xchgw   %cx,%ax                  /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
+	shrb    %cl,%dh	                 /*  */
+	incb    %dh                      /* ending addr is 1 greater than real end */
+	xchgw   %cx,%ax                  /* cx is bank number again */
  /*
   * issue all banks precharge
   */
-bad_reint: 
-        movl    $DRCCTL, %esi            /* setup DRAM control register with */
-        movb    $0x2,%al                 /* All banks precharge */
+bad_reint:
+	movl    $DRCCTL, %esi            /* setup DRAM control register with */
+	movb    $0x2,%al                 /* All banks precharge */
 	movb     %al, (%esi)
-        movl    $CACHELINESZ, %esi       /* address to init read buffer */
+	movl    $CACHELINESZ, %esi       /* address to init read buffer */
 	movw     %ax, (%esi)
 
  /*
   * update ENDING ADDRESS REGISTER
   */
-        movl    $DRCBENDADR, %edi        /* DRAM ending address register */
-        movl    %ecx,%ebx
+	movl    $DRCBENDADR, %edi        /* DRAM ending address register */
+	movl    %ecx,%ebx
 	addl	%ebx, %edi
 	movb    %dh, (%edi)
  /*
   * update CONFIG REGISTER
   */
-        xorb    %dh,%dh
-        movw    $0x00f,%bx
-        movw    %cx,%ax
-        shlw    $2,%ax
-        xchgw   %cx,%ax
-        shlw    %cl,%dx
-        shlw    %cl,%bx
-        notw    %bx
-        xchgw   %cx,%ax
-        movl    $DRCCFG, %edi
+	xorb    %dh,%dh
+	movw    $0x00f,%bx
+	movw    %cx,%ax
+	shlw    $2,%ax
+	xchgw   %cx,%ax
+	shlw    %cl,%dx
+	shlw    %cl,%bx
+	notw    %bx
+	xchgw   %cx,%ax
+	movl    $DRCCFG, %edi
 	mov     (%edi), %ax
-        andw    %bx,%ax
-        orw     %dx,%ax
+	andw    %bx,%ax
+	orw     %dx,%ax
 	movw    %ax, (%edi)
-        jcxz    cleanup
+	jcxz    cleanup
 
-        decw    %cx
-        movl    %ecx,%ebx
-        movl    $DRCBENDADR, %edi        /* DRAM ending address register */
-        movb    $0xff,%al
+	decw    %cx
+	movl    %ecx,%ebx
+	movl    $DRCBENDADR, %edi        /* DRAM ending address register */
+	movb    $0xff,%al
 	addl	%ebx, %edi
 	movb    %al, (%edi)
  /*
-  * set control register to NORMAL mode 
+  * set control register to NORMAL mode
   */
-        movl    $DRCCTL, %esi            /* setup DRAM control register with */
-        movb    $0x0,%al                 /* Normal mode value */
+	movl    $DRCCTL, %esi            /* setup DRAM control register with */
+	movb    $0x0,%al                 /* Normal mode value */
 	movb    %al, (%esi)
-        movl    $CACHELINESZ, %esi       /* address to init read buffer */
+	movl    $CACHELINESZ, %esi       /* address to init read buffer */
 	movw    %ax, (%esi)
-        jmp     nextbank
+	jmp     nextbank
 
-cleanup: 
-        movl    $DRCBENDADR, %edi        /* DRAM ending address register  */
-        movw    $4,%cx
-        xorw    %ax,%ax
-cleanuplp: 
+cleanup:
+	movl    $DRCBENDADR, %edi        /* DRAM ending address register  */
+	movw    $4,%cx
+	xorw    %ax,%ax
+cleanuplp:
 	movb   (%edi), %al
-        orb     %al,%al
-        jz      emptybank
+	orb     %al,%al
+	jz      emptybank
 
-        addb    %ah,%al
-        jns     nottoomuch
+	addb    %ah,%al
+	jns     nottoomuch
 
-        movb    $0x7f,%al
-nottoomuch: 
-        movb    %al,%ah
-        orb     $0x80,%al
+	movb    $0x7f,%al
+nottoomuch:
+	movb    %al,%ah
+	orb     $0x80,%al
 	movb    %al, (%edi)
-emptybank: 
-        incl    %edi
-        loop    cleanuplp
+emptybank:
+	incl    %edi
+	loop    cleanuplp
 
 #if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
 	/* set the CAS latency now since it is hard to do
 	 * when we run from the RAM */
 	movl    $DRCTMCTL, %edi          /* DRAM timing register */
-	movb    (%edi), %al	
+	movb    (%edi), %al
 #ifdef CFG_SDRAM_CAS_LATENCY_2T
 	andb    $0xef, %al
 #endif
 #ifdef CFG_SDRAM_CAS_LATENCY_3T
 	orb     $0x10, %al
-#endif	 
+#endif
 	movb    %al, (%edi)
 #endif
-        movl    $DRCCTL, %edi            /* DRAM Control register */
-        movb    $0x3,%al                 /* Load mode register cmd */
+	movl    $DRCCTL, %edi            /* DRAM Control register */
+	movb    $0x3,%al                 /* Load mode register cmd */
 	movb     %al, (%edi)
 	movw     %ax, (%esi)
 
 
-        movl    $DRCCTL, %edi            /* DRAM Control register */
-        movb    $0x18,%al                /*  Enable refresh and NORMAL mode */
+	movl    $DRCCTL, %edi            /* DRAM Control register */
+	movb    $0x18,%al                /*  Enable refresh and NORMAL mode */
 	movb    %al, (%edi)
 
-        jmp     dram_done
+	jmp     dram_done
+
+bad_ram:
+	xorl    %edx,%edx
+	xorl    %edi,%edi
+	jmp     bad_reint
 
-bad_ram: 
-        xorl    %edx,%edx
-        xorl    %edi,%edi
-        jmp     bad_reint
+dram_done:
 
-dram_done: 
-	
 	/* readback DRCBENDADR and return the number
-	 * of available ram bytes in %eax */ 
+	 * of available ram bytes in %eax */
+
+	movl    $DRCBENDADR, %edi        /* DRAM ending address register  */
 
-        movl    $DRCBENDADR, %edi        /* DRAM ending address register  */
-	
 	movl	(%edi), %eax
 	movl	%eax, %ecx
 	andl	$0x80000000, %ecx
 	jz	bank2
 	andl	$0x7f000000, %eax
-	shrl	$2, %eax 
+	shrl	$2, %eax
 	movl	%eax, %ebx
 
 bank2: 	movl	(%edi), %eax
@@ -509,7 +509,7 @@ bank2: 	movl	(%edi), %eax
 	andl	$0x00800000, %ecx
 	jz	bank1
 	andl	$0x007f0000, %eax
-	shll	$6, %eax 
+	shll	$6, %eax
 	movl	%eax, %ebx
 
 bank1: 	movl	(%edi), %eax
@@ -517,7 +517,7 @@ bank1: 	movl	(%edi), %eax
 	andl	$0x00008000, %ecx
 	jz	bank0
 	andl	$0x00007f00, %eax
-	shll	$14, %eax 
+	shll	$14, %eax
 	movl	%eax, %ebx
 
 bank0: 	movl	(%edi), %eax
@@ -525,7 +525,7 @@ bank0: 	movl	(%edi), %eax
 	andl	$0x00000080, %ecx
 	jz	done
 	andl	$0x0000007f, %eax
-	shll	$22, %eax 
+	shll	$22, %eax
 	movl	%eax, %ebx
 
 done:	movl	%ebx, %eax
diff --git a/cpu/i386/serial.c b/cpu/i386/serial.c
index 22c3c2a..f58b47c 100644
--- a/cpu/i386/serial.c
+++ b/cpu/i386/serial.c
@@ -1,7 +1,7 @@
 /*
  * (C) Copyright 2002
  * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
- * 
+ *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
@@ -81,7 +81,6 @@
 #define asyncLSRRxFifoError1          0x80
 
 
-
 #if CONFIG_SERIAL_SOFTWARE_FIFO
 /*-----------------------------------------------------------------------------+
   | Fifo
@@ -100,7 +99,7 @@ static int serial_buffer_active=0;
 
 static int serial_div(int baudrate)
 {
-	
+
 	switch (baudrate) {
 	case 1200:
 		return 96;
@@ -113,9 +112,9 @@ static int serial_div(int baudrate)
 	case 57600:
 		return 2;
 	case 115200:
-		return 1;		
+		return 1;
 	}
-	
+
 	return 12;
 }
 
@@ -132,7 +131,7 @@ int serial_init(void)
 	volatile char val;
 
 	int bdiv = serial_div(gd->baudrate);
-    
+
 
 	outb(0x80, UART0_BASE + UART_LCR);	/* set DLAB bit */
 	outb(bdiv, UART0_BASE + UART_DLL);	/* set baudrate divisor */
@@ -154,7 +153,7 @@ void serial_setbrg(void)
 	DECLARE_GLOBAL_DATA_PTR;
 
 	unsigned short bdiv;
-	
+
 	bdiv = serial_div(gd->baudrate);
 
 	outb(0x80, UART0_BASE + UART_LCR);	/* set DLAB bit */
@@ -199,7 +198,7 @@ int serial_getc(void)
 		return serial_buffered_getc();
 	}
 #endif
-	
+
 	while (1) {
 #if defined(CONFIG_HW_WATCHDOG)
 		WATCHDOG_RESET();	/* Reset HW Watchdog, if needed */
@@ -262,28 +261,28 @@ void serial_isr(void *arg)
 	} else {
 		space = buf_info.rx_get - rx_put;
 	}
-	
+
 	while (inb(UART0_BASE + UART_LSR) & 1) {
 		c = inb(UART0_BASE);
 		if (space) {
 			buf_info.rx_buffer[rx_put++] = c;
 			space--;
-			
+
 			if (rx_put == buf_info.rx_get) {
 				buf_info.rx_get++;
 				if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
 					buf_info.rx_get = 0;
 				}
 			}
-			
+
 			if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) {
 				rx_put = 0;
 				if (0 == buf_info.rx_get) {
 					buf_info.rx_get = 1;
 				}
-			
+
 			}
-			
+
 		}
 		if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
 			/* Stop flow by setting RTS inactive */
@@ -309,20 +308,20 @@ void serial_buffered_init(void)
 		buf_info.cts = 0;
 	}
 
-	irq_install_handler ( VECNUM_U0 /*UART0 *//*int vec */ ,
+	irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ ,
 			      serial_isr /*interrupt_handler_t *handler */ ,
 			      (void *) &buf_info /*void *arg */ );
 
 	/* Enable "RX Data Available" Interrupt on UART */
 	/* outb(inb(UART0_BASE + UART_IER) |0x01, UART0_BASE + UART_IER); */
 	outb(0x01, UART0_BASE + UART_IER);
-	
+
 	/* Set DTR and RTS active, enable interrupts  */
 	outb(inb (UART0_BASE + UART_MCR) | 0x0b, UART0_BASE + UART_MCR);
-	
+
 	/* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */
 	outb( /*(1 << 6) |*/  1, UART0_BASE + UART_FCR);
-	
+
 	serial_buffer_active = 1;
 }
 
@@ -348,7 +347,7 @@ void serial_buffered_putc (const char c)
 			buf_info.cts = 1;
 		}
 	}
-		
+
 #endif
 	serial_putc (c);
 }
@@ -508,4 +507,3 @@ void kgdb_interruptible(int yes)
 }
 #endif	/* (CONFIG_KGDB_SER_INDEX & 2) */
 #endif	/* CFG_CMD_KGDB */
-
diff --git a/cpu/i386/start.S b/cpu/i386/start.S
index 025555c..afcbb24 100644
--- a/cpu/i386/start.S
+++ b/cpu/i386/start.S
@@ -1,5 +1,5 @@
 /*
- *  U-boot - i386 Startup Code 
+ *  U-boot - i386 Startup Code
  *
  *  Copyright (c) 2002	Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
  *
@@ -26,71 +26,71 @@
 #include <config.h>
 #include <version.h>
 
-	
+
 .section .text
 .code32
 .globl _start
-.type _start, @function	
+.type _start, @function
 .globl _i386boot_start
 _i386boot_start:
-_start:		
-        movl    $0x18,%eax         	/* Load our segement registes, the
-                                         * gdt have already been loaded by start16.S */
-        movw    %ax,%fs
+_start:
+	movl    $0x18,%eax         	/* Load our segement registes, the
+					 * gdt have already been loaded by start16.S */
+	movw    %ax,%fs
 	movw	%ax,%ds
-        movw    %ax,%gs
-        movw    %ax,%es
-        movw    %ax,%ss
-	
+	movw    %ax,%gs
+	movw    %ax,%es
+	movw    %ax,%ss
+
 	/* We call a few functions in the board support package
 	 * since we have no stack yet we'll have to use %ebp
 	 * to store the return address */
-	
+
 	/* Early platform init (setup gpio, etc ) */
 	mov     $early_board_init_ret, %ebp
 	jmp	early_board_init
 early_board_init_ret:
-	
+
 	/* The __port80 entry-point should be usabe by now */
 	/* so we try to indicate progress */
-	movw	$0x01, %ax    
+	movw	$0x01, %ax
 	movl	$.progress0, %ebp
 	jmp	__show_boot_progress
-.progress0:  	
+.progress0:
 
 	/* size memory */
 	mov	$mem_init_ret, %ebp
-	jmp     mem_init		
+	jmp     mem_init
 mem_init_ret:
-	
-	/* check ammount of configured memory 
-	 * (we need atleast bss start+bss size+stack size) */		
+
+	/* check ammount of configured memory
+	 * (we need atleast bss start+bss size+stack size) */
 	movl	$_i386boot_bss_start, %ecx        /* BSS start */
-	addl	$_i386boot_bss_size, %ecx         /* BSS size */	
+	addl	$_i386boot_bss_size, %ecx         /* BSS size */
 	addl	$CFG_STACK_SIZE, %ecx
-	cmpl	%ecx, %eax 
+	cmpl	%ecx, %eax
 	jae	mem_ok
-	
+
 	/* indicate (lack of) progress */
-	movw	$0x81, %ax    
+	movw	$0x81, %ax
 	movl	$.progress0a, %ebp
 	jmp	__show_boot_progress
-.progress0a:  	
+.progress0a:
 	jmp 	die
-mem_ok:	
+mem_ok:
 
 	/* indicate progress */
-	movw	$0x02, %ax    
+	movw	$0x02, %ax
 	movl	$.progress1, %ebp
 	jmp	__show_boot_progress
-.progress1:  	
+.progress1:
 
 	/* create a stack after the bss */
-        movl    $_i386boot_bss_start, %eax
+	movl    $_i386boot_bss_start, %eax
 	addl	$_i386boot_bss_size, %eax
 	addl	$CFG_STACK_SIZE, %eax
-        movl    %eax, %esp
-	
+	movl    %eax, %esp
+
 	pushl	$0
 	popl	%eax
 	cmpl	$0, %eax
@@ -102,83 +102,83 @@ mem_ok:
 
 no_stack:
 	/* indicate (lack of) progress */
-	movw	$0x82, %ax    
+	movw	$0x82, %ax
 	movl	$.progress1a, %ebp
 	jmp	__show_boot_progress
-.progress1a:  	
+.progress1a:
 	jmp die
-	
-	
-stack_ok:	
+
+
+stack_ok:
 	/* indicate progress */
-	movw	$0x03, %ax    
+	movw	$0x03, %ax
 	movl	$.progress2, %ebp
 	jmp	__show_boot_progress
-.progress2:  	
+.progress2:
 
 	/* copy data section to ram, size must be 4-byte aligned */
 	movl	$_i386boot_romdata_dest, %edi	  /* destination address */
- 	movl	$_i386boot_romdata_start, %esi	  /* source address */
+	movl	$_i386boot_romdata_start, %esi	  /* source address */
 	movl	$_i386boot_romdata_size, %ecx     /* number of bytes to copy */
 	movl	%ecx, %eax
 	andl	$3, %eax
 	jnz	data_fail
-	
+
 	shrl	$2, %ecx	                  /* copy 4 byte each time */
-	cld	 
+	cld
 	cmpl	$0, %ecx
-	je	data_ok	
-data_segment:	
-	movsl		
+	je	data_ok
+data_segment:
+	movsl
 	loop	data_segment
 	jmp	data_ok
 data_fail:
 	/* indicate (lack of) progress */
-	movw	$0x83, %ax    
+	movw	$0x83, %ax
 	movl	$.progress2a, %ebp
 	jmp	__show_boot_progress
-.progress2a:  	
+.progress2a:
 	jmp 	die
 
-data_ok:	
+data_ok:
 
 	/* indicate progress */
-	movw	$0x04, %ax    
+	movw	$0x04, %ax
 	movl	$.progress3, %ebp
 	jmp	__show_boot_progress
-.progress3:  	
+.progress3:
 
 	/* clear bss section in ram, size must be 4-byte aligned  */
 	movl	$_i386boot_bss_start, %eax        /* BSS start */
-	movl	$_i386boot_bss_size, %ecx         /* BSS size */	
+	movl	$_i386boot_bss_size, %ecx         /* BSS size */
 	movl	%ecx, %eax
 	andl	$3, %eax
 	jnz	bss_fail
 	shrl	$2, %ecx	                  /* clear 4 byte each time */
-	cld		      
+	cld
 	cmpl	$0, %ecx
-	je	bss_ok	
-bss:	
+	je	bss_ok
+bss:
 	movl	$0, (%edi)
-	add	$4, %edi			
+	add	$4, %edi
 	loop	bss
 	jmp 	bss_ok
 
 bss_fail:
 	/* indicate (lack of) progress */
-	movw	$0x84, %ax    
+	movw	$0x84, %ax
 	movl	$.progress3a, %ebp
 	jmp	__show_boot_progress
-.progress3a:  	
+.progress3a:
 	jmp 	die
 
-bss_ok:	
+bss_ok:
 
-	wbinvd	 
+	wbinvd
 
 
 	/* indicate progress */
-	movw	$0x05, %ax    
+	movw	$0x05, %ax
 	movl	$.progress4, %ebp
 	jmp	__show_boot_progress
 .progress4:
@@ -186,13 +186,11 @@ bss_ok:
 	call	start_i386boot  /* Enter, U-boot! */
 
 	/* indicate (lack of) progress */
-	movw	$0x85, %ax    
+	movw	$0x85, %ax
 	movl	$.progress4a, %ebp
 	jmp	__show_boot_progress
 .progress4a:
 
 die:	hlt
 	jmp	die
-	hlt                     
-
-
+	hlt
diff --git a/cpu/i386/start16.S b/cpu/i386/start16.S
index a34642f..239f2ff 100644
--- a/cpu/i386/start16.S
+++ b/cpu/i386/start16.S
@@ -1,5 +1,5 @@
 /*
- *  U-boot - i386 Startup Code 
+ *  U-boot - i386 Startup Code
  *
  *  Copyright (c) 2002, 2003 Omicron Ceti AB, Daniel Engström <denaiel@omicron.se>
  *
@@ -30,37 +30,37 @@
 .section .start16, "ax"
 .code16
 .globl start16
-start16: 
+start16:
 	/* First we let the BSP do some early initialization
 	 * this code have to map the flash to its final position
 	 */
 	mov	$board_init16_ret, %bp
 	jmp	board_init16
-board_init16_ret:	
-	
+board_init16_ret:
+
 	/* Turn of cache (this might require a 486-class CPU) */
-        movl    %cr0, %eax
-        orl     $0x60000000,%eax
-        movl    %eax, %cr0
-        wbinvd  		     
-	
+	movl    %cr0, %eax
+	orl     $0x60000000,%eax
+	movl    %eax, %cr0
+	wbinvd
+
 	/* load the descriptor tables */
 o32 cs	lidt	idt_ptr
-o32 cs	lgdt    gdt_ptr		 
+o32 cs	lgdt    gdt_ptr
 
 
 	/* Now, we enter protected mode */
-        movl    %cr0, %eax               
-        orl     $1,%eax                  
-        movl    %eax, %cr0            
-	
+	movl    %cr0, %eax
+	orl     $1,%eax
+	movl    %eax, %cr0
+
 	/* Flush the prefetch queue */
-        jmp     ff        
+	jmp     ff
 ff:
 
 	/* Finally jump to the 32bit initialization code */
-	movw	$code32start, %ax 
-        movw    %ax,%bp
+	movw	$code32start, %ax
+	movw    %ax,%bp
 o32 cs	ljmp	*(%bp)
 
 	/* 48-bit far pointer */
@@ -71,17 +71,17 @@ code32start:
 idt_ptr:
 	.word	0				/* limit */
 	.long	0		       		/* base */
-	
+
 gdt_ptr:
 	.word	0x30			        /* limit (48 bytes = 6 GDT entries) */
 	.long	BOOT_SEG + gdt	        	/* base */
 
-	/* The GDT table ... 
+	/* The GDT table ...
 	 *
-	 *       Selector	Type 
+	 *       Selector	Type
 	 * 	 0x00		NULL
 	 * 	 0x08		Unused
-	 *	 0x10		32bit code 
+	 *	 0x10		32bit code
 	 *	 0x18		32bit data/stack
 	 *	 0x20		16bit code
 	 *	 0x28	 	16bit data/stack
@@ -100,12 +100,12 @@ gdt:
 	.word	0x0				/* base address = 0 */
 	.word	0x9300				/* data read/write */
 	.word	0x00CF				/* granularity = 4096, 386 (+5th nibble of limit) */
-						
+
 	.word	0xFFFF				/* 64kb */
 	.word	0				/* base address = 0 */
 	.word	0x9b00				/* data read/write */
 	.word	0x0010				/* granularity = 1  (+5th nibble of limit) */
-	
+
 	.word	0xFFFF				/* 64kb */
 	.word	0				/* base address = 0 */
 	.word	0x9300				/* data read/write */
diff --git a/cpu/i386/timer.c b/cpu/i386/timer.c
index a23cd6e..486d927 100644
--- a/cpu/i386/timer.c
+++ b/cpu/i386/timer.c
@@ -46,28 +46,28 @@ unsigned long get_system_ticks(void)
 int timer_init(void)
 {
 	system_ticks = 0;
-	
+
 	irq_install_handler(0, timer_isr, NULL);
-	
-	/* initialize timer 0 and 2 
-	 * 
+
+	/* initialize timer 0 and 2
+	 *
 	 * Timer 0 is used to increment system_tick 1000 times/sec
 	 * Timer 1 was used for DRAM refresh in early PC's
 	 * Timer 2 is used to drive the speaker
 	 * (to stasrt a beep: write 3 to port 0x61,
 	 * to stop it again: write 0)
 	 */
-		
-        outb(PIT_CMD_CTR0|PIT_CMD_BOTH|PIT_CMD_MODE2, PIT_BASE + PIT_COMMAND);
+
+	outb(PIT_CMD_CTR0|PIT_CMD_BOTH|PIT_CMD_MODE2, PIT_BASE + PIT_COMMAND);
 	outb(TIMER0_VALUE&0xff, PIT_BASE + PIT_T0);
 	outb(TIMER0_VALUE>>8, PIT_BASE + PIT_T0);
 
-        outb(PIT_CMD_CTR2|PIT_CMD_BOTH|PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND);
+	outb(PIT_CMD_CTR2|PIT_CMD_BOTH|PIT_CMD_MODE3, PIT_BASE + PIT_COMMAND);
 	outb(TIMER2_VALUE&0xff, PIT_BASE + PIT_T2);
 	outb(TIMER2_VALUE>>8, PIT_BASE + PIT_T2);
 
 	timer_init_done = 1;
-	
+
 	return 0;
 }
 
@@ -87,7 +87,7 @@ ulong get_timer (ulong base)
 	return (system_ticks - base);
 }
 
-void set_timer (ulong t)	
+void set_timer (ulong t)
 {
 	system_ticks = t;
 }
@@ -102,20 +102,20 @@ static u16 read_pit(void)
 
 /* this is not very exact */
 void udelay (unsigned long usec)
-{	
+{
 	int counter;
 	int wraps;
-	
+
 	if (!timer_init_done) {
 		return;
 	}
 	counter = read_pit();
 	wraps = usec/1000;
 	usec = usec%1000;
-	
+
 	usec*=1194;
 	usec/=1000;
-	usec+=counter; 
+	usec+=counter;
 	if (usec > 1194) {
 		usec-=1194;
 		wraps++;
@@ -123,26 +123,26 @@ void udelay (unsigned long usec)
 
 	while (1) {
 		int new_count = read_pit();
-		
+
 		if (((new_count < usec) && !wraps) || wraps < 0) {
 			break;
 		}
-		
+
 		if (new_count > counter) {
 			wraps--;
 		}
 		counter = new_count;
 	}
-	
+
 }
 
 #if 0
 /* this is a version with debug output */
 void _udelay (unsigned long usec)
-{	
+{
 	int counter;
 	int wraps;
-	
+
 	int usec1, usec2, usec3;
 	int wraps1, wraps2, wraps3, wraps4;
 	int ctr1, ctr2, ctr3, nct1, nct2;
@@ -155,13 +155,13 @@ void _udelay (unsigned long usec)
 	ctr1 = counter;
 	wraps = usec/1000;
 	usec = usec%1000;
-	
+
 	usec2 = usec;
 	wraps1 = wraps;
-	
+
 	usec*=1194;
 	usec/=1000;
-	usec+=counter; 
+	usec+=counter;
 	if (usec > 1194) {
 		usec-=1194;
 		wraps++;
@@ -169,7 +169,7 @@ void _udelay (unsigned long usec)
 
 	usec3 = usec;
 	wraps2 = wraps;
-	
+
 	ctr2 = wraps3 = nct1 = 4711;
 	ctr3 = wraps4 = nct2 = 4711;
 	i=0;
@@ -179,7 +179,7 @@ void _udelay (unsigned long usec)
 		if ((new_count < usec && !wraps) || wraps < 0) {
 			break;
 		}
-		
+
 		if (new_count > counter) {
 			wraps--;
 		}
@@ -192,10 +192,10 @@ void _udelay (unsigned long usec)
 			wraps4 = wraps;
 			nct2 = new_count;
 		}
-		
+
 		counter = new_count;
 	}
-	
+
 	printf("udelay(%d)\n", usec1);
 	printf("counter %d\n", ctr1);
 	printf("1: wraps %d, usec %d\n", wraps1, usec2);