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| author | Mike Nuss <mike@terascala.com> | 2009-10-05 12:33:28 -0400 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2009-10-07 09:10:11 +0200 |
| commit | 54f5f056aa1daa3e39bad1c5c3fb43a72cdb9e84 (patch) | |
| tree | 049354d5e1f2fac5642865ee2078e6b8d29b4449 /cpu/blackfin | |
| parent | 99dbd4efd6d5ecc37d7e8f28b20d9be8c83055c7 (diff) | |
| download | u-boot-imx-54f5f056aa1daa3e39bad1c5c3fb43a72cdb9e84.zip u-boot-imx-54f5f056aa1daa3e39bad1c5c3fb43a72cdb9e84.tar.gz u-boot-imx-54f5f056aa1daa3e39bad1c5c3fb43a72cdb9e84.tar.bz2 | |
PPC4xx: Denali core: Fix incorrect DDR row bits
The SPD detection code for the Denali memory controller used on some
ppc4xx
processors incorrectly encodes DDR0_42. With certain memory
configurations,
this can cause the bootwrapper to incorrectly calculate the installed
memory
size, because the number of row bits is wrong. This patch fixes that
encoding.
Signed-off-by: Mike Nuss <mike@terascala.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'cpu/blackfin')
0 files changed, 0 insertions, 0 deletions