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| author | Dave Liu <daveliu@freescale.com> | 2009-02-25 12:31:32 +0800 |
|---|---|---|
| committer | Kim Phillips <kim.phillips@freescale.com> | 2009-03-05 18:20:37 -0600 |
| commit | 5b0055547f0246908b79cc300170d87380b69e18 (patch) | |
| tree | 6141a20ef84fbfdab53d5747fe482896c31ad694 /cpu/blackfin/start.S | |
| parent | b7be63abec45858c044f0fbd6aeef524c4663f9b (diff) | |
| download | u-boot-imx-5b0055547f0246908b79cc300170d87380b69e18.zip u-boot-imx-5b0055547f0246908b79cc300170d87380b69e18.tar.gz u-boot-imx-5b0055547f0246908b79cc300170d87380b69e18.tar.bz2 | |
83xx: Fix some bugs in spd sdram code
1. RD_TO_PRE missed to add the AL, and need min 2 clocks for
tRTP according to DDR2 JEDEC spec.
2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec.
3. add the support of DDR2-533,667,800 DIMMs
4. cpo
5. make the AL to min to gain better performance.
The Micron MT9HTF6472CHY-667D1 DIMMs test passed on
MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate.
items 1, 2 and 5:
Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'cpu/blackfin/start.S')
0 files changed, 0 insertions, 0 deletions