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authorMike Frysinger <vapier@gentoo.org>2009-04-04 08:40:13 -0400
committerMike Frysinger <vapier@gentoo.org>2009-04-06 17:37:48 -0400
commit8ef929afa43c77c9573caa57c6e17a97a33775c0 (patch)
tree06f917337ccae6ecda40a1dc43118bba7f2ca3a4 /cpu/blackfin/initcode.c
parentc2e07449f546fb375289cdac1a608fdc20357873 (diff)
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Blackfin: add check for anomaly 05000362
DESCRIPTION: The column address width settings for banks 2 and 3 are misconnected in the SDRAM controller. Accesses to bank 2 will result in an error if the Column Address Width for bank 3 (EB3CAW ) is not set to be the same as that of bank 2. WORKAROUND: If using bank 2, make sure that banks 2 and 3 have the same column address width settings in the EBIU_SDBCTL register. This must be the case regardless of whether or not bank 3 is enabled. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'cpu/blackfin/initcode.c')
-rw-r--r--cpu/blackfin/initcode.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/cpu/blackfin/initcode.c b/cpu/blackfin/initcode.c
index 062cbb8..aba00e0 100644
--- a/cpu/blackfin/initcode.c
+++ b/cpu/blackfin/initcode.c
@@ -246,6 +246,15 @@ static inline void serial_putc(char c)
#endif
#endif
+/* Conflicting Column Address Widths Causes SDRAM Errors:
+ * EB2CAW and EB3CAW must be the same
+ */
+#if ANOMALY_05000362
+# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
+# error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
+# endif
+#endif
+
BOOTROM_CALLED_FUNC_ATTR
void initcode(ADI_BOOT_DATA *bootstruct)
{