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author | Peter Tyser <ptyser@xes-inc.com> | 2010-04-12 22:28:13 -0500 |
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committer | Wolfgang Denk <wd@denx.de> | 2010-04-13 09:13:25 +0200 |
commit | c6fb83d21729321426308c3acff2a3dfb20d250b (patch) | |
tree | 85b569582345fdd9361d8524df08e92251c84a59 /cpu/blackfin/cache.S | |
parent | a4145534851bf74619cb373a942613a74547bb82 (diff) | |
download | u-boot-imx-c6fb83d21729321426308c3acff2a3dfb20d250b.zip u-boot-imx-c6fb83d21729321426308c3acff2a3dfb20d250b.tar.gz u-boot-imx-c6fb83d21729321426308c3acff2a3dfb20d250b.tar.bz2 |
blackfin: Move cpu/blackfin/* to arch/blackfin/cpu/*
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Diffstat (limited to 'cpu/blackfin/cache.S')
-rw-r--r-- | cpu/blackfin/cache.S | 87 |
1 files changed, 0 insertions, 87 deletions
diff --git a/cpu/blackfin/cache.S b/cpu/blackfin/cache.S deleted file mode 100644 index 6ed655a..0000000 --- a/cpu/blackfin/cache.S +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Blackfin cache control code - * - * Copyright 2003-2008 Analog Devices Inc. - * - * Enter bugs at http://blackfin.uclinux.org/ - * - * Licensed under the GPL-2 or later. - */ - -#include <asm/linkage.h> -#include <config.h> -#include <asm/blackfin.h> - -.text -/* Since all L1 caches work the same way, we use the same method for flushing - * them. Only the actual flush instruction differs. We write this in asm as - * GCC can be hard to coax into writing nice hardware loops. - * - * Also, we assume the following register setup: - * R0 = start address - * R1 = end address - */ -.macro do_flush flushins:req optflushins optnopins label - - R2 = -L1_CACHE_BYTES; - - /* start = (start & -L1_CACHE_BYTES) */ - R0 = R0 & R2; - - /* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */ - R1 += -1; - R1 = R1 & R2; - R1 += L1_CACHE_BYTES; - - /* count = (end - start) >> L1_CACHE_SHIFT */ - R2 = R1 - R0; - R2 >>= L1_CACHE_SHIFT; - P1 = R2; - -.ifnb \label -\label : -.endif - P0 = R0; - LSETUP (1f, 2f) LC1 = P1; -1: -.ifnb \optflushins - \optflushins [P0]; -.endif -#if ANOMALY_05000443 -.ifb \optnopins -2: -.endif - \flushins [P0++]; -.ifnb \optnopins -2: \optnopins; -.endif -#else -2: \flushins [P0++]; -#endif - - RTS; -.endm - -/* Invalidate all instruction cache lines assocoiated with this memory area */ -ENTRY(_blackfin_icache_flush_range) - do_flush IFLUSH, , nop -ENDPROC(_blackfin_icache_flush_range) - -/* Flush all cache lines assocoiated with this area of memory. */ -ENTRY(_blackfin_icache_dcache_flush_range) - do_flush FLUSH, IFLUSH -ENDPROC(_blackfin_icache_dcache_flush_range) - -/* Throw away all D-cached data in specified region without any obligation to - * write them back. Since the Blackfin ISA does not have an "invalidate" - * instruction, we use flush/invalidate. Perhaps as a speed optimization we - * could bang on the DTEST MMRs ... - */ -ENTRY(_blackfin_dcache_flush_invalidate_range) - do_flush FLUSHINV -ENDPROC(_blackfin_dcache_flush_invalidate_range) - -/* Flush all data cache lines assocoiated with this memory area */ -ENTRY(_blackfin_dcache_flush_range) - do_flush FLUSH, , , .Ldfr -ENDPROC(_blackfin_dcache_flush_range) |