Merge branch 'master' of git://www.denx.de/git/u-boot-blackfin

Conflicts:

	Makefile
	doc/README.standalone

Signed-off-by: Wolfgang Denk <wd@denx.de>

13 files changed, 100 insertions, 128 deletions

diff --git a/cpu/bf561/Makefile b/cpu/bf561/Makefile
index 2947169..418a437 100644
--- a/cpu/bf561/Makefile
+++ b/cpu/bf561/Makefile
@@ -28,12 +28,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).a
 
-START	= start.o start1.o interrupt.o cache.o flush.o init_sdram.o
+SOBJS	= start.o start1.o interrupt.o cache.o flush.o init_sdram.o
 COBJS	= cpu.o traps.o ints.o serial.o interrupts.o video.o
 
 EXTRA = init_sdram_bootrom_initblock.o
 
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 START	:= $(addprefix $(obj),$(START))
 
diff --git a/cpu/bf561/cache.S b/cpu/bf561/cache.S
index 5bda5bf..d9015c6 100644
--- a/cpu/bf561/cache.S
+++ b/cpu/bf561/cache.S
@@ -2,6 +2,7 @@
 #include <asm/linkage.h>
 #include <config.h>
 #include <asm/blackfin.h>
+#include <asm/mach-common/bits/mpu.h>
 
 .text
 .align 2
diff --git a/cpu/bf561/config.mk b/cpu/bf561/config.mk
index f4dc04b..3628a02 100644
--- a/cpu/bf561/config.mk
+++ b/cpu/bf561/config.mk
@@ -24,4 +24,4 @@
 # MA 02110-1301 USA
 #
 
-PLATFORM_RELFLAGS += -mcpu=bf561 -ffixed-P5
+PLATFORM_RELFLAGS += -mcpu=bf561
diff --git a/cpu/bf561/cpu.c b/cpu/bf561/cpu.c
index 5b907cd..e0dd2f5 100644
--- a/cpu/bf561/cpu.c
+++ b/cpu/bf561/cpu.c
@@ -40,7 +40,7 @@ extern unsigned int dcplb_table[page_descriptor_table_size][2];
 
 int do_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_ISRAM)
+	__asm__ __volatile__("cli r3;" "P0 = %0;" "JUMP (P0);"::"r"(L1_INST_SRAM)
 	    );
 
 	return 0;
@@ -100,22 +100,18 @@ void icache_enable(void)
 
 	}
 
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-	sync();
-	sti();
+	SSYNC();
 }
 
 void icache_disable(void)
 {
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-	sync();
-	sti();
+	SSYNC();
 }
 
 int icache_status(void)
@@ -175,14 +171,12 @@ void dcache_enable(void)
 		}
 	}
 
-	cli();
 	temp = *(unsigned int *)DMEM_CONTROL;
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL =
 	    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | temp;
-	sync();
-	sti();
+	SSYNC();
 }
 
 void dcache_disable(void)
@@ -191,13 +185,11 @@ void dcache_disable(void)
 	unsigned int *I0, *I1;
 	int i;
 
-	cli();
-	sync();
+	SSYNC();
 	asm(" .align 8; ");
 	*(unsigned int *)DMEM_CONTROL &=
 	    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-	sync();
-	sti();
+	SSYNC();
 
 	/* after disable dcache, clear it so we don't confuse the next application */
 	I0 = (unsigned int *)DCPLB_ADDR0;
diff --git a/cpu/bf561/init_sdram.S b/cpu/bf561/init_sdram.S
index d763f27..f5ccf30 100644
--- a/cpu/bf561/init_sdram.S
+++ b/cpu/bf561/init_sdram.S
@@ -4,6 +4,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #include <asm/mem_init.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
 .global init_sdram;
 
 #if (CONFIG_CCLK_DIV == 1)
diff --git a/cpu/bf561/init_sdram_bootrom_initblock.S b/cpu/bf561/init_sdram_bootrom_initblock.S
index 5e3c88a..9cc5e78 100644
--- a/cpu/bf561/init_sdram_bootrom_initblock.S
+++ b/cpu/bf561/init_sdram_bootrom_initblock.S
@@ -4,6 +4,10 @@
 #include <config.h>
 #include <asm/blackfin.h>
 #include <asm/mem_init.h>
+#include <asm/mach-common/bits/bootrom.h>
+#include <asm/mach-common/bits/ebiu.h>
+#include <asm/mach-common/bits/pll.h>
+#include <asm/mach-common/bits/uart.h>
 .global init_sdram;
 
 #if (CONFIG_CCLK_DIV == 1)
diff --git a/cpu/bf561/interrupt.S b/cpu/bf561/interrupt.S
index 21839ce..a10eaab 100644
--- a/cpu/bf561/interrupt.S
+++ b/cpu/bf561/interrupt.S
@@ -42,9 +42,7 @@
 #define ASSEMBLY
 #include <config.h>
 #include <asm/blackfin.h>
-#include <asm/hw_irq.h>
 #include <asm/entry.h>
-#include <asm/blackfin_defs.h>
 
 .global _blackfin_irq_panic;
 
@@ -55,7 +53,7 @@
 .global _evt_emulation
 _evt_emulation:
 	SAVE_CONTEXT
-	r0 = IRQ_EMU;
+	r0 = 0;
 	r1 = seqstat;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -66,7 +64,7 @@ _evt_emulation:
 .global _evt_nmi
 _evt_nmi:
 	SAVE_CONTEXT
-	r0 = IRQ_NMI;
+	r0 = 2;
 	r1 = RETN;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -88,7 +86,7 @@ _trap:
 .global _evt_rst
 _evt_rst:
 	SAVE_CONTEXT
-	r0 = IRQ_RST;
+	r0 = 1;
 	r1 = RETN;
 	sp += -12;
 	call _do_reset;
@@ -98,7 +96,7 @@ _evt_rst_exit:
 	rtn;
 
 irq_panic:
-	r0 = IRQ_EVX;
+	r0 = 3;
 	r1 =  sp;
 	sp += -12;
 	call _blackfin_irq_panic;
@@ -115,7 +113,7 @@ _evt_ivhw_exit:
 .global _evt_timer
 _evt_timer:
 	SAVE_CONTEXT
-	r0 = IRQ_CORETMR;
+	r0 = 6;
 	sp += -12;
 	/* Polling method used now. */
 	/* call timer_int; */
diff --git a/cpu/bf561/interrupts.c b/cpu/bf561/interrupts.c
index ecbc6ad..7880061 100644
--- a/cpu/bf561/interrupts.c
+++ b/cpu/bf561/interrupts.c
@@ -35,8 +35,6 @@
  */
 
 #include <common.h>
-#include <asm/machdep.h>
-#include <asm/irq.h>
 #include <config.h>
 #include <asm/blackfin.h>
 #include "cpu.h"
@@ -72,12 +70,10 @@ ulong get_tbclk(void)
 
 void enable_interrupts(void)
 {
-	restore_flags(int_flag);
 }
 
 int disable_interrupts(void)
 {
-	save_and_cli(int_flag);
 	return 1;
 }
 
diff --git a/cpu/bf561/ints.c b/cpu/bf561/ints.c
index 27a38a3..d6aa393 100644
--- a/cpu/bf561/ints.c
+++ b/cpu/bf561/ints.c
@@ -39,12 +39,9 @@
 #include <common.h>
 #include <linux/stddef.h>
 #include <asm/system.h>
-#include <asm/irq.h>
 #include <asm/traps.h>
 #include <asm/io.h>
 #include <asm/errno.h>
-#include <asm/machdep.h>
-#include <asm/setup.h>
 #include <asm/blackfin.h>
 #include "cpu.h"
 
@@ -61,42 +58,40 @@ void blackfin_irq_panic(int reason, struct pt_regs *regs)
 
 void blackfin_init_IRQ(void)
 {
-	*(unsigned volatile long *)(SIC_IMASK) = SIC_UNMASK_ALL;
-	cli();
+	*(unsigned volatile long *)(SICA_IMASK0) = 0;
 #ifndef CONFIG_KGDB
-	*(unsigned volatile long *)(EVT_EMULATION_ADDR) = 0x0;
+	*(unsigned volatile long *)(EVT1) = 0x0;
 #endif
-	*(unsigned volatile long *)(EVT_NMI_ADDR) =
+	*(unsigned volatile long *)(EVT2) =
 	    (unsigned volatile long)evt_nmi;
-	*(unsigned volatile long *)(EVT_EXCEPTION_ADDR) =
+	*(unsigned volatile long *)(EVT3) =
 	    (unsigned volatile long)trap;
-	*(unsigned volatile long *)(EVT_HARDWARE_ERROR_ADDR) =
+	*(unsigned volatile long *)(EVT5) =
 	    (unsigned volatile long)evt_ivhw;
-	*(unsigned volatile long *)(EVT_RESET_ADDR) =
+	*(unsigned volatile long *)(EVT0) =
 	    (unsigned volatile long)evt_rst;
-	*(unsigned volatile long *)(EVT_TIMER_ADDR) =
+	*(unsigned volatile long *)(EVT6) =
 	    (unsigned volatile long)evt_timer;
-	*(unsigned volatile long *)(EVT_IVG7_ADDR) =
+	*(unsigned volatile long *)(EVT7) =
 	    (unsigned volatile long)evt_evt7;
-	*(unsigned volatile long *)(EVT_IVG8_ADDR) =
+	*(unsigned volatile long *)(EVT8) =
 	    (unsigned volatile long)evt_evt8;
-	*(unsigned volatile long *)(EVT_IVG9_ADDR) =
+	*(unsigned volatile long *)(EVT9) =
 	    (unsigned volatile long)evt_evt9;
-	*(unsigned volatile long *)(EVT_IVG10_ADDR) =
+	*(unsigned volatile long *)(EVT10) =
 	    (unsigned volatile long)evt_evt10;
-	*(unsigned volatile long *)(EVT_IVG11_ADDR) =
+	*(unsigned volatile long *)(EVT11) =
 	    (unsigned volatile long)evt_evt11;
-	*(unsigned volatile long *)(EVT_IVG12_ADDR) =
+	*(unsigned volatile long *)(EVT12) =
 	    (unsigned volatile long)evt_evt12;
-	*(unsigned volatile long *)(EVT_IVG13_ADDR) =
+	*(unsigned volatile long *)(EVT13) =
 	    (unsigned volatile long)evt_evt13;
-	*(unsigned volatile long *)(EVT_IVG14_ADDR) =
+	*(unsigned volatile long *)(EVT14) =
 	    (unsigned volatile long)evt_system_call;
-	*(unsigned volatile long *)(EVT_IVG15_ADDR) =
+	*(unsigned volatile long *)(EVT15) =
 	    (unsigned volatile long)evt_soft_int1;
 	*(volatile unsigned long *)ILAT = 0;
 	asm("csync;");
-	sti();
 	*(volatile unsigned long *)IMASK = 0xffbf;
 	asm("csync;");
 }
diff --git a/cpu/bf561/serial.c b/cpu/bf561/serial.c
index bc5a4f5..a398fd5 100644
--- a/cpu/bf561/serial.c
+++ b/cpu/bf561/serial.c
@@ -43,14 +43,12 @@
  */
 
 #include <common.h>
-#include <asm/irq.h>
 #include <asm/system.h>
-#include <asm/segment.h>
 #include <asm/bitops.h>
 #include <asm/delay.h>
-#include <asm/uaccess.h>
 #include "serial.h"
 #include <asm/io.h>
+#include <asm/mach-common/bits/uart.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -85,32 +83,32 @@ void serial_setbrg(void)
 	}
 
 	/* Enable UART */
-	*pUART_GCTL |= UART_GCTL_UCEN;
-	sync();
+	*pUART_GCTL |= UCEN;
+	SSYNC();
 
 	/* Set DLAB in LCR to Access DLL and DLH */
 	ACCESS_LATCH;
-	sync();
+	SSYNC();
 
 	*pUART_DLL = hw_baud_table[i].dl_low;
-	sync();
+	SSYNC();
 	*pUART_DLH = hw_baud_table[i].dl_high;
-	sync();
+	SSYNC();
 
 	/* Clear DLAB in LCR to Access THR RBR IER */
 	ACCESS_PORT_IER;
-	sync();
+	SSYNC();
 
 	/*
 	 * Enable  ERBFI and ELSI interrupts
 	 * to poll SIC_ISR register
 	 */
-	*pUART_IER = UART_IER_ELSI | UART_IER_ERBFI | UART_IER_ETBEI;
-	sync();
+	*pUART_IER = ELSI | ERBFI | ETBEI;
+	SSYNC();
 
 	/* Set LCR to Word Lengh 8-bit word select */
-	*pUART_LCR = UART_LCR_WLS8;
-	sync();
+	*pUART_LCR = WLS_8;
+	SSYNC();
 
 	return;
 }
@@ -123,14 +121,14 @@ int serial_init(void)
 
 void serial_putc(const char c)
 {
-	if ((*pUART_LSR) & UART_LSR_TEMT) {
+	if ((*pUART_LSR) & TEMT) {
 		if (c == '\n')
 			serial_putc('\r');
 
 		local_put_char(c);
 	}
 
-	while (!((*pUART_LSR) & UART_LSR_TEMT))
+	while (!((*pUART_LSR) & TEMT))
 		SYNC_ALL;
 
 	return;
@@ -138,7 +136,7 @@ void serial_putc(const char c)
 
 int serial_tstc(void)
 {
-	if (*pUART_LSR & UART_LSR_DR)
+	if (*pUART_LSR & DR)
 		return 1;
 	else
 		return 0;
@@ -151,14 +149,14 @@ int serial_getc(void)
 	int ret;
 
 	/* Poll for RX Interrupt */
-	while (!((isr_val =
-		  *(volatile unsigned long *)SIC_ISR) & IRQ_UART_RX_BIT)) ;
+	while (!serial_tstc())
+		continue;
 	asm("csync;");
 
 	uart_lsr_val = *pUART_LSR;	/* Clear status bit */
 	uart_rbr_val = *pUART_RBR;	/* getc() */
 
-	if (isr_val & IRQ_UART_ERROR_BIT) {
+	if (uart_lsr_val & (OE|PE|FE|BI)) {
 		ret = -1;
 	} else {
 		ret = uart_rbr_val & 0xff;
@@ -179,19 +177,12 @@ static void local_put_char(char ch)
 	int flags = 0;
 	unsigned long isr_val;
 
-	save_and_cli(flags);
-
 	/* Poll for TX Interruput */
-	while (!((isr_val = *pSIC_ISR) & IRQ_UART_TX_BIT)) ;
+	while (!(*pUART_LSR & THRE))
+		continue;
 	asm("csync;");
 
 	*pUART_THR = ch;	/* putc() */
 
-	if (isr_val & IRQ_UART_ERROR_BIT) {
-		printf("?");
-	}
-
-	restore_flags(flags);
-
 	return;
 }
diff --git a/cpu/bf561/serial.h b/cpu/bf561/serial.h
index c1cbf36..647560c 100644
--- a/cpu/bf561/serial.h
+++ b/cpu/bf561/serial.h
@@ -49,8 +49,8 @@
 #include <asm/blackfin.h>
 
 #define SYNC_ALL	__asm__ __volatile__ ("ssync;\n")
-#define ACCESS_LATCH	*pUART_LCR |= UART_LCR_DLAB;
-#define ACCESS_PORT_IER	*pUART_LCR &= (~UART_LCR_DLAB);
+#define ACCESS_LATCH	*pUART_LCR |= DLAB;
+#define ACCESS_PORT_IER	*pUART_LCR &= (~DLAB);
 
 void serial_setbrg(void);
 static void local_put_char(char ch);
diff --git a/cpu/bf561/start.S b/cpu/bf561/start.S
index bd26cf3..6565de8 100644
--- a/cpu/bf561/start.S
+++ b/cpu/bf561/start.S
@@ -41,17 +41,16 @@
 #include <config.h>
 #include <asm/blackfin.h>
 
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/dma.h>
+#include <asm/mach-common/bits/pll.h>
+
 .global _stext;
 .global __bss_start;
 .global start;
 .global _start;
-.global _rambase;
-.global _ramstart;
-.global _ramend;
 .global edata;
-.global _initialize;
 .global _exit;
-.global flashdataend;
 .global init_sdram;
 
 .text
@@ -127,16 +126,16 @@ no_soft_reset:
 	nop;
 
 	/* Clear EVT registers */
-	p0.h = (EVT_EMULATION_ADDR >> 16);
-	p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
+	p0.h = (EVT0 >> 16);
+	p0.l = (EVT0 & 0xFFFF);
 	p0 += 8;
 	p1 = 14;
 	r1 = 0;
 	LSETUP(4,4) lc0 = p1;
 	[ p0 ++ ] = r1;
 
-	p0.h = hi(SIC_IWR);
-	p0.l = lo(SIC_IWR);
+	p0.h = hi(SICA_IWR0);
+	p0.l = lo(SICA_IWR0);
 	r0.l = 0x1;
 	w[p0] = r0.l;
 	SSYNC;
@@ -193,8 +192,8 @@ loop1:
 	 */
 
 	/* To keep ourselves in the supervisor mode */
-	p0.l = (EVT_IVG15_ADDR & 0xFFFF);
-	p0.h = (EVT_IVG15_ADDR >> 16);
+	p0.l = (EVT15 & 0xFFFF);
+	p0.h = (EVT15 >> 16);
 
 	p1.l = _real_start;
 	p1.h = _real_start;
@@ -202,8 +201,8 @@ loop1:
 
 	p0.l = (IMASK & 0xFFFF);
 	p0.h = (IMASK >> 16);
-	r0.l = LO(IVG15_POS);
-	r0.h = HI(IVG15_POS);
+	r0.l = LO(EVT_IVG15);
+	r0.h = HI(EVT_IVG15);
 	[p0] = r0;
 	raise 15;
 	p0.l = WAIT_HERE;
@@ -218,13 +217,6 @@ WAIT_HERE:
 _real_start:
 	[ -- sp ] = reti;
 
-#ifdef CONFIG_EZKIT561
-	p0.l = (WDOG_CTL & 0xFFFF);
-	p0.h = (WDOG_CTL >> 16);
-	r0 = WATCHDOG_DISABLE(z);
-	w[p0] = r0;
-#endif
-
 	/* DMA reset code to Hi of L1 SRAM */
 copy:
 	P1.H = hi(SYSMMR_BASE);	/* P1 Points to the beginning of SYSTEM MMR Space */
@@ -235,37 +227,37 @@ copy:
 	R1.H = reset_end;
 	R1.L = reset_end;
 	R2 = R1 - R0;		/* Count */
-	R1.H = hi(L1_ISRAM);	/* Destination Address (high) */
-	R1.L = lo(L1_ISRAM);	/* Destination Address (low) */
+	R1.H = hi(L1_INST_SRAM);	/* Destination Address (high) */
+	R1.L = lo(L1_INST_SRAM);	/* Destination Address (low) */
 	R3.L = DMAEN;		/* Source DMAConfig Value (8-bit words) */
 	R4.L = (DI_EN | WNR | DMAEN);	/* Destination DMAConfig Value (8-bit words) */
 
 DMA:
 	R6 = 0x1 (Z);
-	W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
-	W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
+	W[P1+OFFSET_(IMDMA_S0_X_MODIFY)] = R6;	/* Source Modify = 1 */
+	W[P1+OFFSET_(IMDMA_D0_X_MODIFY)] = R6;	/* Destination Modify = 1 */
 
-	[P1+OFFSET_(MDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
-	W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
+	[P1+OFFSET_(IMDMA_S0_START_ADDR)] = R0;	/* Set Source Base Address */
+	W[P1+OFFSET_(IMDMA_S0_X_COUNT)] = R2;	/* Set Source Count */
 	/* Set Source  DMAConfig = DMA Enable,
 	Memory Read,  8-Bit Transfers, 1-D DMA, Flow - Stop */
-	W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
+	W[P1+OFFSET_(IMDMA_S0_CONFIG)] = R3;
 
-	[P1+OFFSET_(MDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
-	W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
+	[P1+OFFSET_(IMDMA_D0_START_ADDR)] = R1;	/* Set Destination Base Address */
+	W[P1+OFFSET_(IMDMA_D0_X_COUNT)] = R2;	/* Set Destination Count */
 	/* Set Destination DMAConfig = DMA Enable,
 	Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
-	W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
+	W[P1+OFFSET_(IMDMA_D0_CONFIG)] = R4;
 
 WAIT_DMA_DONE:
-	p0.h = hi(MDMA_D0_IRQ_STATUS);
-	p0.l = lo(MDMA_D0_IRQ_STATUS);
+	p0.h = hi(IMDMA_D0_IRQ_STATUS);
+	p0.l = lo(IMDMA_D0_IRQ_STATUS);
 	R0 = W[P0](Z);
 	CC = BITTST(R0, 0);
 	if ! CC jump WAIT_DMA_DONE
 
 	R0 = 0x1;
-	W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
+	W[P1+OFFSET_(IMDMA_D0_IRQ_STATUS)] = R0;	/* Write 1 to clear DMA interrupt */
 
 	/* Initialize BSS Section with 0 s */
 	p1.l = __bss_start;
diff --git a/cpu/bf561/traps.c b/cpu/bf561/traps.c
index 7e2dcd1..e35620c 100644
--- a/cpu/bf561/traps.c
+++ b/cpu/bf561/traps.c
@@ -36,14 +36,13 @@
 #include <common.h>
 #include <linux/types.h>
 #include <asm/errno.h>
-#include <asm/irq.h>
 #include <asm/system.h>
 #include <asm/traps.h>
-#include <asm/machdep.h>
 #include "cpu.h"
-#include <asm/arch/anomaly.h>
 #include <asm/cplb.h>
 #include <asm/io.h>
+#include <asm/mach-common/bits/core.h>
+#include <asm/mach-common/bits/mpu.h>
 
 void init_IRQ(void)
 {
@@ -68,7 +67,7 @@ static unsigned int cplb_sizes[4] =
 void trap_c(struct pt_regs *regs)
 {
 	unsigned int addr;
-	unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
+	unsigned long trapnr = (regs->seqstat) & EXCAUSE;
 	unsigned int i, j, size, *I0, *I1;
 	unsigned short data = 0;
 
@@ -76,7 +75,7 @@ void trap_c(struct pt_regs *regs)
 		/* 0x26 - Data CPLB Miss */
 	case VEC_CPLB_M:
 
-#ifdef ANOMALY_05000261
+#if ANOMALY_05000261
 		/*
 		 * Work around an anomaly: if we see a new DCPLB fault, return
 		 * without doing anything.  Then, if we get the same fault again,
@@ -118,16 +117,16 @@ void trap_c(struct pt_regs *regs)
 
 		/* Turn the cache off */
 		if (data) {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL &=
 			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-			sync();
+			SSYNC();
 		}
 
 		if (data) {
@@ -173,16 +172,16 @@ void trap_c(struct pt_regs *regs)
 		/* Turn the cache back on */
 		if (data) {
 			j = *(unsigned int *)DMEM_CONTROL;
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL =
 			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
-			sync();
+			SSYNC();
 		} else {
-			sync();
+			SSYNC();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-			sync();
+			SSYNC();
 		}
 
 		break;