[Blackfin][PATCH] code cleanup

1 files changed, 35 insertions, 45 deletions

diff --git a/cpu/bf533/traps.c b/cpu/bf533/traps.c
index 5e2ce9b..248e34f 100644
--- a/cpu/bf533/traps.c
+++ b/cpu/bf533/traps.c
@@ -44,16 +44,7 @@
 #include "cpu.h"
 #include <asm/arch/anomaly.h>
 #include <asm/cplb.h>
-
-#ifdef DEBUG
-#define pr_debug(fmt,arg...)  printf(fmt,##arg)
-#else
-static inline int
-    __attribute__ ((format(printf, 1, 2))) pr_debug(const char *fmt, ...)
-{
-	return 0;
-}
-#endif
+#include <asm/io.h>
 
 void init_IRQ(void)
 {
@@ -83,13 +74,13 @@ void trap_c(struct pt_regs *regs)
 	unsigned short data = 0;
 
 	switch (trapnr) {
-		/* 0x26 - Data CPLB Miss */
+	/* 0x26 - Data CPLB Miss */
 	case VEC_CPLB_M:
 
 #ifdef ANOMALY_05000261
 		/*
-		 * Work around an anomaly: if we see a new DCPLB fault, 
-		 * return without doing anything. Then, 
+		 * Work around an anomaly: if we see a new DCPLB fault,
+		 * return without doing anything. Then,
 		 * if we get the same fault again, handle it.
 		 */
 		addr = last_cplb_fault_retx;
@@ -104,9 +95,9 @@ void trap_c(struct pt_regs *regs)
 	case VEC_CPLB_I_M:
 
 		if (data) {
-			addr = *pDCPLB_FAULT_ADDR;
+			addr = *(unsigned int *)pDCPLB_FAULT_ADDR;
 		} else {
-			addr = *pICPLB_FAULT_ADDR;
+			addr = *(unsigned int *)pICPLB_FAULT_ADDR;
 		}
 		for (i = 0; i < page_descriptor_table_size; i++) {
 			if (data) {
@@ -117,7 +108,7 @@ void trap_c(struct pt_regs *regs)
 				j = icplb_table[i][0];
 			}
 			if ((j <= addr) && ((j + size) > addr)) {
-				pr_debug("found %i 0x%08x\n", i, j);
+				debug("found %i 0x%08x\n", i, j);
 				break;
 			}
 		}
@@ -128,16 +119,16 @@ void trap_c(struct pt_regs *regs)
 
 		/* Turn the cache off */
 		if (data) {
-			__builtin_bfin_ssync();
+			sync();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL &=
 			    ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
-			__builtin_bfin_ssync();
+			sync();
 		} else {
-			__builtin_bfin_ssync();
+			sync();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
-			__builtin_bfin_ssync();
+			sync();
 		}
 
 		if (data) {
@@ -150,16 +141,16 @@ void trap_c(struct pt_regs *regs)
 
 		j = 0;
 		while (*I1 & CPLB_LOCK) {
-			pr_debug("skipping %i %08p - %08x\n", j, I1, *I1);
+			debug("skipping %i %08p - %08x\n", j, I1, *I1);
 			*I0++;
 			*I1++;
 			j++;
 		}
 
-		pr_debug("remove %i 0x%08x  0x%08x\n", j, *I0, *I1);
+		debug("remove %i 0x%08x  0x%08x\n", j, *I0, *I1);
 
 		for (; j < 15; j++) {
-			pr_debug("replace %i 0x%08x  0x%08x\n", j, I0, I0 + 1);
+			debug("replace %i 0x%08x  0x%08x\n", j, I0, I0 + 1);
 			*I0++ = *(I0 + 1);
 			*I1++ = *(I1 + 1);
 		}
@@ -177,22 +168,22 @@ void trap_c(struct pt_regs *regs)
 		}
 
 		for (j = 0; j < 16; j++) {
-			pr_debug("%i 0x%08x  0x%08x\n", j, *I0++, *I1++);
+			debug("%i 0x%08x  0x%08x\n", j, *I0++, *I1++);
 		}
 
 		/* Turn the cache back on */
 		if (data) {
 			j = *(unsigned int *)DMEM_CONTROL;
-			__builtin_bfin_ssync();
+			sync();
 			asm(" .align 8; ");
 			*(unsigned int *)DMEM_CONTROL =
 			    ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
-			__builtin_bfin_ssync();
+			sync();
 		} else {
-			__builtin_bfin_ssync();
+			sync();
 			asm(" .align 8; ");
 			*(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
-			__builtin_bfin_ssync();
+			sync();
 		}
 
 		break;
@@ -209,42 +200,41 @@ void trap_c(struct pt_regs *regs)
 		do_reset(NULL, 0, 0, NULL);
 	}
 
-      trap_c_return:
 	return;
 
 }
 
 void dump(struct pt_regs *fp)
 {
-	pr_debug("RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n",
+	debug("RETE:  %08lx  RETN: %08lx  RETX: %08lx  RETS: %08lx\n",
 		 fp->rete, fp->retn, fp->retx, fp->rets);
-	pr_debug("IPEND: %04lx  SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
-	pr_debug("SEQSTAT: %08lx    SP: %08lx\n", (long)fp->seqstat, (long)fp);
-	pr_debug("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
+	debug("IPEND: %04lx  SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
+	debug("SEQSTAT: %08lx    SP: %08lx\n", (long)fp->seqstat, (long)fp);
+	debug("R0: %08lx    R1: %08lx    R2: %08lx    R3: %08lx\n",
 		 fp->r0, fp->r1, fp->r2, fp->r3);
-	pr_debug("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
+	debug("R4: %08lx    R5: %08lx    R6: %08lx    R7: %08lx\n",
 		 fp->r4, fp->r5, fp->r6, fp->r7);
-	pr_debug("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
+	debug("P0: %08lx    P1: %08lx    P2: %08lx    P3: %08lx\n",
 		 fp->p0, fp->p1, fp->p2, fp->p3);
-	pr_debug("P4: %08lx    P5: %08lx    FP: %08lx\n",
+	debug("P4: %08lx    P5: %08lx    FP: %08lx\n",
 		 fp->p4, fp->p5, fp->fp);
-	pr_debug("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
+	debug("A0.w: %08lx    A0.x: %08lx    A1.w: %08lx    A1.x: %08lx\n",
 		 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
 
-	pr_debug("LB0: %08lx  LT0: %08lx  LC0: %08lx\n",
+	debug("LB0: %08lx  LT0: %08lx  LC0: %08lx\n",
 		 fp->lb0, fp->lt0, fp->lc0);
-	pr_debug("LB1: %08lx  LT1: %08lx  LC1: %08lx\n",
+	debug("LB1: %08lx  LT1: %08lx  LC1: %08lx\n",
 		 fp->lb1, fp->lt1, fp->lc1);
-	pr_debug("B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n",
+	debug("B0: %08lx  L0: %08lx  M0: %08lx  I0: %08lx\n",
 		 fp->b0, fp->l0, fp->m0, fp->i0);
-	pr_debug("B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n",
+	debug("B1: %08lx  L1: %08lx  M1: %08lx  I1: %08lx\n",
 		 fp->b1, fp->l1, fp->m1, fp->i1);
-	pr_debug("B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n",
+	debug("B2: %08lx  L2: %08lx  M2: %08lx  I2: %08lx\n",
 		 fp->b2, fp->l2, fp->m2, fp->i2);
-	pr_debug("B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n",
+	debug("B3: %08lx  L3: %08lx  M3: %08lx  I3: %08lx\n",
 		 fp->b3, fp->l3, fp->m3, fp->i3);
 
-	pr_debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
-	pr_debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
+	debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
+	debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
 
 }