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| author | Aubrey Li <aubrey.adi@gmail.com> | 2007-03-12 12:11:55 +0800 |
|---|---|---|
| committer | Aubrey Li <aubrey.adi@gmail.com> | 2007-03-12 12:11:55 +0800 |
| commit | 0d93de11449390a5984b0236c3612e50f6dbb7e8 (patch) | |
| tree | 2a18b53c26f2fd52427bc8d592a59d741848b646 /cpu/bf533/start.S | |
| parent | bfa5754a58477ac917d21527cd0f079d87cf188e (diff) | |
| download | u-boot-imx-0d93de11449390a5984b0236c3612e50f6dbb7e8.zip u-boot-imx-0d93de11449390a5984b0236c3612e50f6dbb7e8.tar.gz u-boot-imx-0d93de11449390a5984b0236c3612e50f6dbb7e8.tar.bz2 | |
[Blackfin][PATCH] minor cleanup
Diffstat (limited to 'cpu/bf533/start.S')
| -rw-r--r-- | cpu/bf533/start.S | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/cpu/bf533/start.S b/cpu/bf533/start.S index 3a31e2f..94556d6 100644 --- a/cpu/bf533/start.S +++ b/cpu/bf533/start.S @@ -82,7 +82,7 @@ _stext: SSYNC; /* As per HW reference manual DAG registers, - * DATA and Address resgister shall be zero'd + * DATA and Address resgister shall be zero'd * in initialization, after a reset state */ r1 = 0; /* Data registers zero'd */ @@ -99,7 +99,7 @@ _stext: p3 = 0; p4 = 0; p5 = 0; - + i0 = 0; /* DAG Registers zero'd */ i1 = 0; i2 = 0; @@ -150,7 +150,7 @@ no_soft_reset: r1 = 0; LSETUP(4,4) lc0 = p1; [ p0 ++ ] = r1; - + p0.h = hi(SIC_IWR); p0.l = lo(SIC_IWR); r0.l = 0x1; @@ -259,8 +259,8 @@ DMA: /* Set Destination DMAConfig = DMA Enable, Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */ W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4; - -WAIT_DMA_DONE: + +WAIT_DMA_DONE: p0.h = hi(MDMA_D0_IRQ_STATUS); p0.l = lo(MDMA_D0_IRQ_STATUS); R0 = W[P0](Z); |