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| author | Aubrey Li <aubrey.adi@gmail.com> | 2007-03-10 23:49:29 +0800 |
|---|---|---|
| committer | Aubrey Li <aubrey.adi@gmail.com> | 2007-03-10 23:49:29 +0800 |
| commit | 8db13d63157811c839d15a313d9f2d2f5fd10af3 (patch) | |
| tree | e8f94f4059122b3218cffe1d3bbe577aea6cb6d9 /cpu/bf533/cache.S | |
| parent | ef26a08fef928b7bc11ae2c109e638dc3a016d91 (diff) | |
| download | u-boot-imx-8db13d63157811c839d15a313d9f2d2f5fd10af3.zip u-boot-imx-8db13d63157811c839d15a313d9f2d2f5fd10af3.tar.gz u-boot-imx-8db13d63157811c839d15a313d9f2d2f5fd10af3.tar.bz2 | |
[Blackfin][PATCH] code cleanup
Diffstat (limited to 'cpu/bf533/cache.S')
| -rw-r--r-- | cpu/bf533/cache.S | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/cpu/bf533/cache.S b/cpu/bf533/cache.S index d2b34a9..5dcc24f 100644 --- a/cpu/bf533/cache.S +++ b/cpu/bf533/cache.S @@ -68,7 +68,7 @@ ENTRY(_invalidate_entire_icache) (R7:5) =[SP++]; RTS; -/* +/* * Invalidate the Entire Data cache by * clearing DMC[1:0] bits */ @@ -80,7 +80,7 @@ ENTRY(_dcache_invalidate) P0.H = (DMEM_CONTROL >> 16); R7 =[P0]; -/* +/* * Clear the DMC[1:0] bits, All valid bits in the data * cache are set to the invalid state */ @@ -118,7 +118,7 @@ ENTRY(_blackfin_dcache_invalidate_range) CC = P0 < P1(iu); IF CC JUMP 1b(bp); -/* +/* * If the data crosses a cache line, then we'll be pointing to * the last cache line, but won't have flushed/invalidated it yet, so do * one more. |