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| author | wdenk <wdenk> | 2004-07-10 21:45:47 +0000 |
|---|---|---|
| committer | wdenk <wdenk> | 2004-07-10 21:45:47 +0000 |
| commit | 8b07a1103dc7dcadc80c4a9681cfa7d225e8e224 (patch) | |
| tree | 8017b2826d62ec6d8289b8f1170627dc5c21ffcf /cpu/at91rm9200 | |
| parent | 0ac6f8b7498d3608bd1de2280a014e9e23d7b1f2 (diff) | |
| download | u-boot-imx-8b07a1103dc7dcadc80c4a9681cfa7d225e8e224.zip u-boot-imx-8b07a1103dc7dcadc80c4a9681cfa7d225e8e224.tar.gz u-boot-imx-8b07a1103dc7dcadc80c4a9681cfa7d225e8e224.tar.bz2 | |
* Patch by Fred Klatt, 25 Jun 2004:
Add support for WindRiver's SBC8560 board
* Patch by Nicolas Lacressonniere, 24 Jun 2004
Small Bugs fixes for "at91rm9200dk" board:
- Timing modifications for SPI DataFlash access
- Fix NAND flash detection bug
* Patch by Nicolas Lacressonniere, 24 Jun 2004:
Add Support for Flash AT49BV6416 for AT91RM9200DK board
Diffstat (limited to 'cpu/at91rm9200')
| -rw-r--r-- | cpu/at91rm9200/at45.c | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/cpu/at91rm9200/at45.c b/cpu/at91rm9200/at45.c index 9dfe560..3c00132 100644 --- a/cpu/at91rm9200/at45.c +++ b/cpu/at91rm9200/at45.c @@ -25,7 +25,14 @@ #ifdef CONFIG_HAS_DATAFLASH #include <dataflash.h> -#define SPI_CLK 5000000 +#define AT91C_SPI_CLK 10000000 /* Max Value = 10MHz to be compliant to +the Continuous Array Read function */ + +/* AC Characteristics */ +/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */ +#define DATAFLASH_TCSS (0xC << 16) +#define DATAFLASH_TCHS (0x1 << 24) + #define AT91C_TIMEOUT_WRDY 200000 #define AT91C_SPI_PCS0_SERIAL_DATAFLASH 0xE /* Chip Select 0 : NPCS0 %1110 */ #define AT91C_SPI_PCS3_DATAFLASH_CARD 0x7 /* Chip Select 3 : NPCS3 %0111 */ @@ -50,9 +57,11 @@ void AT91F_SpiInit(void) { AT91C_BASE_SPI->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS; /* Configure CS0 and CS3 */ - *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & 0x100000) | ((AT91C_MASTER_CLOCK / (2*SPI_CLK)) << 8); + *(AT91C_SPI_CSR + 0) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); - *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & 0x100000) | ((AT91C_MASTER_CLOCK / (2*SPI_CLK)) << 8); + *(AT91C_SPI_CSR + 3) = AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) | (AT91C_SPI_DLYBCT & + DATAFLASH_TCHS) | ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8); } |