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authorwdenk <wdenk>2004-11-24 23:35:19 +0000
committerwdenk <wdenk>2004-11-24 23:35:19 +0000
commited54e6212518262d27abe5e6de3c608d5ebceafb (patch)
tree81a904f4473e7425023cfd2da4415b9f7fdfe10b /cpu/at91rm9200
parentbb310d462bbe2be9be867f969e7a2b60ae90e785 (diff)
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* Fix udelay() on AT91RM9200 for delays < 1 ms.
* Enable long help on CMC PU2 board; fix reset issue; increase CPU speed from 179 to 207 MHz.
Diffstat (limited to 'cpu/at91rm9200')
-rw-r--r--cpu/at91rm9200/cpu.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/cpu/at91rm9200/cpu.c b/cpu/at91rm9200/cpu.c
index a464f29..71463c9 100644
--- a/cpu/at91rm9200/cpu.c
+++ b/cpu/at91rm9200/cpu.c
@@ -134,12 +134,26 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
/*shutdown the console to avoid strange chars during reset */
us->US_CR = (AT91C_US_RSTRX | AT91C_US_RSTTX);
+#ifdef CONFIG_AT91RM9200DK
/* Clear PA19 to trigger the hard reset */
pio->PIO_CODR = 0x00080000;
pio->PIO_OER = 0x00080000;
pio->PIO_PER = 0x00080000;
+#endif
+#ifdef CONFIG_CMC_PU2
+/* this is the way Linux does it */
+#define AT91C_ST_RSTEN (0x1 << 16)
+#define AT91C_ST_EXTEN (0x1 << 17)
+#define AT91C_ST_WDRST (0x1 << 0)
+/* watchdog mode register */
+#define ST_WDMR *((unsigned long *)0xfffffd08)
+/* system clock control register */
+#define ST_CR *((unsigned long *)0xfffffd00)
+ ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
+ ST_CR = AT91C_ST_WDRST;
/* Never reached */
#endif
+#endif
return 0;
}