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authorwdenk <wdenk>2005-04-04 12:23:03 +0000
committerwdenk <wdenk>2005-04-04 12:23:03 +0000
commitba83a3076523be79e85fd07433f8b3f361e6428b (patch)
tree0a916f274e8999de8f1c9760e7c836d7486cd17a /cpu/at91rm9200
parent101e8dfa2a8b045c6655bf2b3d6fba8d378453cd (diff)
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Patch by Steven Scholz, 04 Apr 2005:
Make sure that MDIO clock does not exceed 2.5 MHz on AT91
Diffstat (limited to 'cpu/at91rm9200')
-rw-r--r--cpu/at91rm9200/at91rm9200_ether.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/cpu/at91rm9200/at91rm9200_ether.c b/cpu/at91rm9200/at91rm9200_ether.c
index 2ec888f..0bc1d89 100644
--- a/cpu/at91rm9200/at91rm9200_ether.c
+++ b/cpu/at91rm9200/at91rm9200_ether.c
@@ -210,6 +210,11 @@ int eth_init (bd_t * bd)
p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
#endif
+#if (AT91C_MASTER_CLOCK > 40000000)
+ /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
+ p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
+#endif
+
p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
at91rm92000_GetPhyInterface (& PhyOps);