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authorwdenk <wdenk>2004-11-21 00:06:33 +0000
committerwdenk <wdenk>2004-11-21 00:06:33 +0000
commit9d5028c2f7a65d3777867a6cfc966a01a5823132 (patch)
treec971cc2b0d41e422585c1911fffda7d2d6403ee4 /cpu/at91rm9200/start.S
parentcacfab588a897c369a4906818c5ed4bc40a450c5 (diff)
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* Update for AT91RM9200DK and CMC_PU2 boards:
- Enable booting directly from flash - fix CMC_PU2 flash driver * Fix mkimage usage message
Diffstat (limited to 'cpu/at91rm9200/start.S')
-rw-r--r--cpu/at91rm9200/start.S67
1 files changed, 65 insertions, 2 deletions
diff --git a/cpu/at91rm9200/start.S b/cpu/at91rm9200/start.S
index d73af20..4f1d9ae 100644
--- a/cpu/at91rm9200/start.S
+++ b/cpu/at91rm9200/start.S
@@ -112,9 +112,53 @@ reset:
*/
mrs r0,cpsr
bic r0,r0,#0x1f
- orr r0,r0,#0x13
+ orr r0,r0,#0xd3 /* was 13 */
msr cpsr,r0
+#ifdef CONFIG_BOOTBINFUNC
+/* code based on entry.S from ATMEL */
+#define AT91C_BASE_CKGR 0xFFFFFC20
+#define CKGR_MOR 0
+ /* Get the CKGR Base Address */
+ ldr r1, =AT91C_BASE_CKGR
+
+/* Main oscillator Enable register APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF */
+/* ldr r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT */
+ ldr r0, =0x0000FF01
+ str r0, [r1, #CKGR_MOR]
+ /* Add loop to compensate Main Oscillator startup time */
+ ldr r0, =0x00000010
+LoopOsc:
+ subs r0, r0, #1
+ bhi LoopOsc
+
+ /* scratch stack */
+ ldr r1, =0x00204000
+ /* Insure word alignment */
+ bic r1, r1, #3
+ /* Init stack SYS */
+ mov sp, r1
+ /*
+ * This does a lot more than just set up the memory, which
+ * is why it's called lowlevelinit
+ */
+ bl lowlevelinit /* in memsetup.S */
+ bl icache_enable;
+ /*------------------------------------
+ Read/modify/write CP15 control register
+ -------------------------------------
+ read cp15 control register (cp15 r1) in r0
+ ------------------------------------*/
+ mrc p15, 0, r0, c1, c0, 0
+ /* Reset bit :Little Endian end fast bus mode */
+ ldr r3, =0xC0000080
+ /* Set bit :Asynchronous clock mode, Not Fast Bus */
+ ldr r4, =0xC0000000
+ bic r0, r0, r3
+ orr r0, r0, r4
+ /* write r0 in cp15 control register (cp15 r1) */
+ mcr p15, 0, r0, c1, c0, 0
+#endif /* CONFIG_BOOTBINFUNC */
/*
* relocate exeception table
*/
@@ -135,6 +179,25 @@ copyex:
bl cpu_init_crit
#endif
+#ifdef CONFIG_BOOTBINFUNC
+relocate: /* relocate U-Boot to RAM */
+ adr r0, _start /* r0 <- current position of code */
+ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
+
+ ldr r2, _armboot_start
+ ldr r3, _bss_start
+ sub r2, r3, r2 /* r2 <- size of armboot */
+ add r2, r0, r2 /* r2 <- source end address */
+
+copy_loop:
+ ldmia r0!, {r3-r10} /* copy from source address [r0] */
+ stmia r1!, {r3-r10} /* copy to target address [r1] */
+ cmp r0, r2 /* until source end addreee [r2] */
+ ble copy_loop
+#endif /* CONFIG_BOOTBINFUNC */
+
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
@@ -168,7 +231,7 @@ _start_armboot: .word start_armboot
*/
cpu_init_crit:
- # actually do nothing for now!
+ /* do nothing for now */
mov pc, lr