Merge branch 'master' of git://www.denx.de/git/u-boot

15 files changed, 365 insertions, 992 deletions

diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile
index f69b1f3..33dc427 100644
--- a/cpu/at32ap/Makefile
+++ b/cpu/at32ap/Makefile
@@ -27,13 +27,18 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(CPU).a
 
-START	:= start.o
-SOBJS	:= entry.o
-COBJS	:= cpu.o hsdramc.o exception.o cache.o
-COBJS	+= interrupts.o pio.o atmel_mci.o
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-START	:= $(addprefix $(obj),$(START))
+START-y			+= start.o
+
+COBJS-y			+= cpu.o
+COBJS-y			+= hsdramc.o
+COBJS-y			+= exception.o
+COBJS-y			+= cache.o
+COBJS-y			+= interrupts.o
+COBJS-y			+= pio.o
+
+SRCS	:= $(START-y:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
+START	:= $(addprefix $(obj),$(START-y))
 
 all: $(obj).depend $(START) $(LIB)
 
diff --git a/cpu/at32ap/at32ap700x/Makefile b/cpu/at32ap/at32ap700x/Makefile
index d276712..7404235 100644
--- a/cpu/at32ap/at32ap700x/Makefile
+++ b/cpu/at32ap/at32ap700x/Makefile
@@ -24,7 +24,7 @@ include $(TOPDIR)/config.mk
 
 LIB	:= $(obj)lib$(SOC).a
 
-COBJS	:= gpio.o
+COBJS	:= gpio.o clk.o
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c
new file mode 100644
index 0000000..b3aa034
--- /dev/null
+++ b/cpu/at32ap/at32ap700x/clk.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2005-2008 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+
+#include <asm/arch/clk.h>
+#include <asm/arch/memory-map.h>
+
+#include "sm.h"
+
+void clk_init(void)
+{
+	uint32_t cksel;
+
+	/* in case of soft resets, disable watchdog */
+	sm_writel(WDT_CTRL, SM_BF(KEY, 0x55));
+	sm_writel(WDT_CTRL, SM_BF(KEY, 0xaa));
+
+#ifdef CONFIG_PLL
+	/* Initialize the PLL */
+	sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
+			    | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
+			    | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
+			    | SM_BF(PLLOPT, CFG_PLL0_OPT)
+			    | SM_BF(PLLOSC, 0)
+			    | SM_BIT(PLLEN)));
+
+	/* Wait for lock */
+	while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
+#endif
+
+	/* Set up clocks for the CPU and all peripheral buses */
+	cksel = 0;
+	if (CFG_CLKDIV_CPU)
+		cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
+	if (CFG_CLKDIV_HSB)
+		cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
+	if (CFG_CLKDIV_PBA)
+		cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
+	if (CFG_CLKDIV_PBB)
+		cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
+	sm_writel(PM_CKSEL, cksel);
+
+#ifdef CONFIG_PLL
+	/* Use PLL0 as main clock */
+	sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
+#endif
+}
diff --git a/cpu/at32ap/at32ap700x/gpio.c b/cpu/at32ap/at32ap700x/gpio.c
index 859124a..56ba2f9 100644
--- a/cpu/at32ap/at32ap700x/gpio.c
+++ b/cpu/at32ap/at32ap700x/gpio.c
@@ -21,8 +21,11 @@
  */
 #include <common.h>
 
+#include <asm/io.h>
+
 #include <asm/arch/chip-features.h>
 #include <asm/arch/gpio.h>
+#include <asm/arch/memory-map.h>
 
 /*
  * Lots of small functions here. We depend on --gc-sections getting
@@ -142,3 +145,55 @@ void gpio_enable_mmci(void)
 	gpio_select_periph_A(GPIO_PIN_PA15, 0);	/* DATA3 */
 }
 #endif
+
+#ifdef AT32AP700x_CHIP_HAS_SPI
+void gpio_enable_spi0(unsigned long cs_mask)
+{
+	gpio_select_periph_A(GPIO_PIN_PA0,  0);	/* MISO	*/
+	gpio_select_periph_A(GPIO_PIN_PA1,  0);	/* MOSI	*/
+	gpio_select_periph_A(GPIO_PIN_PA2,  0);	/* SCK	*/
+
+	/* Set up NPCSx as GPIO outputs, initially high */
+	if (cs_mask & (1 << 0)) {
+		gpio_set_value(GPIO_PIN_PA3, 1);
+		gpio_select_pio(GPIO_PIN_PA3, GPIOF_OUTPUT);
+	}
+	if (cs_mask & (1 << 1)) {
+		gpio_set_value(GPIO_PIN_PA4, 1);
+		gpio_select_pio(GPIO_PIN_PA4, GPIOF_OUTPUT);
+	}
+	if (cs_mask & (1 << 2)) {
+		gpio_set_value(GPIO_PIN_PA5, 1);
+		gpio_select_pio(GPIO_PIN_PA5, GPIOF_OUTPUT);
+	}
+	if (cs_mask & (1 << 3)) {
+		gpio_set_value(GPIO_PIN_PA20, 1);
+		gpio_select_pio(GPIO_PIN_PA20, GPIOF_OUTPUT);
+	}
+}
+
+void gpio_enable_spi1(unsigned long cs_mask)
+{
+	gpio_select_periph_B(GPIO_PIN_PA0,  0);	/* MISO	*/
+	gpio_select_periph_B(GPIO_PIN_PB1,  0);	/* MOSI	*/
+	gpio_select_periph_B(GPIO_PIN_PB5,  0);	/* SCK	*/
+
+	/* Set up NPCSx as GPIO outputs, initially high */
+	if (cs_mask & (1 << 0)) {
+		gpio_set_value(GPIO_PIN_PB2, 1);
+		gpio_select_pio(GPIO_PIN_PB2, GPIOF_OUTPUT);
+	}
+	if (cs_mask & (1 << 1)) {
+		gpio_set_value(GPIO_PIN_PB3, 1);
+		gpio_select_pio(GPIO_PIN_PB3, GPIOF_OUTPUT);
+	}
+	if (cs_mask & (1 << 2)) {
+		gpio_set_value(GPIO_PIN_PB4, 1);
+		gpio_select_pio(GPIO_PIN_PB4, GPIOF_OUTPUT);
+	}
+	if (cs_mask & (1 << 3)) {
+		gpio_set_value(GPIO_PIN_PA27, 1);
+		gpio_select_pio(GPIO_PIN_PA27, GPIOF_OUTPUT);
+	}
+}
+#endif
diff --git a/cpu/at32ap/sm.h b/cpu/at32ap/at32ap700x/sm.h
index 6492c8e..6492c8e 100644
--- a/cpu/at32ap/sm.h
+++ b/cpu/at32ap/at32ap700x/sm.h
diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c
deleted file mode 100644
index f59dfb5..0000000
--- a/cpu/at32ap/atmel_mci.c
+++ /dev/null
@@ -1,550 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-
-#ifdef CONFIG_MMC
-
-#include <part.h>
-#include <mmc.h>
-
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <asm/byteorder.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/memory-map.h>
-
-#include "atmel_mci.h"
-
-#ifdef DEBUG
-#define pr_debug(fmt, args...) printf(fmt, ##args)
-#else
-#define pr_debug(...) do { } while(0)
-#endif
-
-#ifndef CFG_MMC_CLK_OD
-#define CFG_MMC_CLK_OD		150000
-#endif
-
-#ifndef CFG_MMC_CLK_PP
-#define CFG_MMC_CLK_PP		5000000
-#endif
-
-#ifndef CFG_MMC_OP_COND
-#define CFG_MMC_OP_COND		0x00100000
-#endif
-
-#define MMC_DEFAULT_BLKLEN	512
-#define MMC_DEFAULT_RCA		1
-
-static unsigned int mmc_rca;
-static int mmc_card_is_sd;
-static block_dev_desc_t mmc_blkdev;
-
-block_dev_desc_t *mmc_get_dev(int dev)
-{
-	return &mmc_blkdev;
-}
-
-static void mci_set_mode(unsigned long hz, unsigned long blklen)
-{
-	unsigned long bus_hz;
-	unsigned long clkdiv;
-
-	bus_hz = get_mci_clk_rate();
-	clkdiv = (bus_hz / hz) / 2 - 1;
-
-	pr_debug("mmc: setting clock %lu Hz, block size %lu\n",
-		 hz, blklen);
-
-	if (clkdiv & ~255UL) {
-		clkdiv = 255;
-		printf("mmc: clock %lu too low; setting CLKDIV to 255\n",
-			hz);
-	}
-
-	blklen &= 0xfffc;
-	mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv)
-			 | MMCI_BF(BLKLEN, blklen)
-			 | MMCI_BIT(RDPROOF)
-			 | MMCI_BIT(WRPROOF)));
-}
-
-#define RESP_NO_CRC	1
-#define R1		MMCI_BF(RSPTYP, 1)
-#define R2		MMCI_BF(RSPTYP, 2)
-#define R3		(R1 | RESP_NO_CRC)
-#define R6		R1
-#define NID		MMCI_BF(MAXLAT, 0)
-#define NCR		MMCI_BF(MAXLAT, 1)
-#define TRCMD_START	MMCI_BF(TRCMD, 1)
-#define TRDIR_READ	MMCI_BF(TRDIR, 1)
-#define TRTYP_BLOCK	MMCI_BF(TRTYP, 0)
-#define INIT_CMD	MMCI_BF(SPCMD, 1)
-#define OPEN_DRAIN	MMCI_BF(OPDCMD, 1)
-
-#define ERROR_FLAGS	(MMCI_BIT(DTOE)			\
-			 | MMCI_BIT(RDIRE)		\
-			 | MMCI_BIT(RENDE)		\
-			 | MMCI_BIT(RINDE)		\
-			 | MMCI_BIT(RTOE))
-
-static int
-mmc_cmd(unsigned long cmd, unsigned long arg,
-	void *resp, unsigned long flags)
-{
-	unsigned long *response = resp;
-	int i, response_words = 0;
-	unsigned long error_flags;
-	u32 status;
-
-	pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n",
-		 cmd, arg, flags);
-
-	error_flags = ERROR_FLAGS;
-	if (!(flags & RESP_NO_CRC))
-		error_flags |= MMCI_BIT(RCRCE);
-
-	flags &= ~MMCI_BF(CMDNB, ~0UL);
-
-	if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_48_BIT_RESP)
-		response_words = 1;
-	else if (MMCI_BFEXT(RSPTYP, flags) == MMCI_RSPTYP_136_BIT_RESP)
-		response_words = 4;
-
-	mmci_writel(ARGR, arg);
-	mmci_writel(CMDR, cmd | flags);
-	do {
-		udelay(40);
-		status = mmci_readl(SR);
-	} while (!(status & MMCI_BIT(CMDRDY)));
-
-	pr_debug("mmc: status 0x%08lx\n", status);
-
-	if (status & ERROR_FLAGS) {
-		printf("mmc: command %lu failed (status: 0x%08lx)\n",
-		       cmd, status);
-		return -EIO;
-	}
-
-	if (response_words)
-		pr_debug("mmc: response:");
-
-	for (i = 0; i < response_words; i++) {
-		response[i] = mmci_readl(RSPR);
-		pr_debug(" %08lx", response[i]);
-	}
-	pr_debug("\n");
-
-	return 0;
-}
-
-static int mmc_acmd(unsigned long cmd, unsigned long arg,
-		    void *resp, unsigned long flags)
-{
-	unsigned long aresp[4];
-	int ret;
-
-	/*
-	 * Seems like the APP_CMD part of an ACMD has 64 cycles max
-	 * latency even though the ACMD part doesn't. This isn't
-	 * entirely clear in the SD Card spec, but some cards refuse
-	 * to work if we attempt to use 5 cycles max latency here...
-	 */
-	ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp,
-		      R1 | NCR | (flags & OPEN_DRAIN));
-	if (ret)
-		return ret;
-	if ((aresp[0] & (R1_ILLEGAL_COMMAND | R1_APP_CMD)) != R1_APP_CMD)
-		return -ENODEV;
-
-	ret = mmc_cmd(cmd, arg, resp, flags);
-	return ret;
-}
-
-static unsigned long
-mmc_bread(int dev, unsigned long start, lbaint_t blkcnt,
-	  unsigned long *buffer)
-{
-	int ret, i = 0;
-	unsigned long resp[4];
-	unsigned long card_status, data;
-	unsigned long wordcount;
-	u32 status;
-
-	if (blkcnt == 0)
-		return 0;
-
-	pr_debug("mmc_bread: dev %d, start %lx, blkcnt %lx\n",
-		 dev, start, blkcnt);
-
-	/* Put the device into Transfer state */
-	ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR);
-	if (ret) goto out;
-
-	/* Set block length */
-	ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR);
-	if (ret) goto out;
-
-	pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR));
-
-	for (i = 0; i < blkcnt; i++, start++) {
-		ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK,
-			      start * mmc_blkdev.blksz, resp,
-			      (R1 | NCR | TRCMD_START | TRDIR_READ
-			       | TRTYP_BLOCK));
-		if (ret) goto out;
-
-		ret = -EIO;
-		wordcount = 0;
-		do {
-			do {
-				status = mmci_readl(SR);
-				if (status & (ERROR_FLAGS | MMCI_BIT(OVRE)))
-					goto read_error;
-			} while (!(status & MMCI_BIT(RXRDY)));
-
-			if (status & MMCI_BIT(RXRDY)) {
-				data = mmci_readl(RDR);
-				/* pr_debug("%x\n", data); */
-				*buffer++ = data;
-				wordcount++;
-			}
-		} while(wordcount < (mmc_blkdev.blksz / 4));
-
-		pr_debug("mmc: read %u words, waiting for BLKE\n", wordcount);
-
-		do {
-			status = mmci_readl(SR);
-		} while (!(status & MMCI_BIT(BLKE)));
-
-		putc('.');
-	}
-
-out:
-	/* Put the device back into Standby state */
-	mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR);
-	return i;
-
-read_error:
-	mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR);
-	printf("mmc: bread failed, status = %08x, card status = %08x\n",
-	       status, card_status);
-	goto out;
-}
-
-static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp)
-{
-	cid->mid = resp[0] >> 24;
-	cid->oid = (resp[0] >> 8) & 0xffff;
-	cid->pnm[0] = resp[0];
-	cid->pnm[1] = resp[1] >> 24;
-	cid->pnm[2] = resp[1] >> 16;
-	cid->pnm[3] = resp[1] >> 8;
-	cid->pnm[4] = resp[1];
-	cid->pnm[5] = resp[2] >> 24;
-	cid->pnm[6] = 0;
-	cid->prv = resp[2] >> 16;
-	cid->psn = (resp[2] << 16) | (resp[3] >> 16);
-	cid->mdt = resp[3] >> 8;
-}
-
-static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp)
-{
-	cid->mid = resp[0] >> 24;
-	cid->oid = (resp[0] >> 8) & 0xffff;
-	cid->pnm[0] = resp[0];
-	cid->pnm[1] = resp[1] >> 24;
-	cid->pnm[2] = resp[1] >> 16;
-	cid->pnm[3] = resp[1] >> 8;
-	cid->pnm[4] = resp[1];
-	cid->pnm[5] = 0;
-	cid->pnm[6] = 0;
-	cid->prv = resp[2] >> 24;
-	cid->psn = (resp[2] << 8) | (resp[3] >> 24);
-	cid->mdt = (resp[3] >> 8) & 0x0fff;
-}
-
-static void mmc_dump_cid(const struct mmc_cid *cid)
-{
-	printf("Manufacturer ID:       %02lX\n", cid->mid);
-	printf("OEM/Application ID:    %04lX\n", cid->oid);
-	printf("Product name:          %s\n", cid->pnm);
-	printf("Product Revision:      %lu.%lu\n",
-	       cid->prv >> 4, cid->prv & 0x0f);
-	printf("Product Serial Number: %lu\n", cid->psn);
-	printf("Manufacturing Date:    %02lu/%02lu\n",
-	       cid->mdt >> 4, cid->mdt & 0x0f);
-}
-
-static void mmc_dump_csd(const struct mmc_csd *csd)
-{
-	unsigned long *csd_raw = (unsigned long *)csd;
-	printf("CSD data: %08lx %08lx %08lx %08lx\n",
-	       csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]);
-	printf("CSD structure version:   1.%u\n", csd->csd_structure);
-	printf("MMC System Spec version: %u\n", csd->spec_vers);
-	printf("Card command classes:    %03x\n", csd->ccc);
-	printf("Read block length:       %u\n", 1 << csd->read_bl_len);
-	if (csd->read_bl_partial)
-		puts("Supports partial reads\n");
-	else
-		puts("Does not support partial reads\n");
-	printf("Write block length:      %u\n", 1 << csd->write_bl_len);
-	if (csd->write_bl_partial)
-		puts("Supports partial writes\n");
-	else
-		puts("Does not support partial writes\n");
-	if (csd->wp_grp_enable)
-		printf("Supports group WP:      %u\n", csd->wp_grp_size + 1);
-	else
-		puts("Does not support group WP\n");
-	printf("Card capacity:		%u bytes\n",
-	       (csd->c_size + 1) * (1 << (csd->c_size_mult + 2)) *
-	       (1 << csd->read_bl_len));
-	printf("File format:            %u/%u\n",
-	       csd->file_format_grp, csd->file_format);
-	puts("Write protection:        ");
-	if (csd->perm_write_protect)
-		puts(" permanent");
-	if (csd->tmp_write_protect)
-		puts(" temporary");
-	putc('\n');
-}
-
-static int mmc_idle_cards(void)
-{
-	int ret;
-
-	/* Reset and initialize all cards */
-	ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
-	if (ret)
-		return ret;
-
-	/* Keep the bus idle for 74 clock cycles */
-	return mmc_cmd(0, 0, NULL, INIT_CMD);
-}
-
-static int sd_init_card(struct mmc_cid *cid, int verbose)
-{
-	unsigned long resp[4];
-	int i, ret = 0;
-
-	mmc_idle_cards();
-	for (i = 0; i < 1000; i++) {
-		ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND,
-			       resp, R3 | NID);
-		if (ret || (resp[0] & 0x80000000))
-			break;
-		ret = -ETIMEDOUT;
-	}
-
-	if (ret)
-		return ret;
-
-	ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID);
-	if (ret)
-		return ret;
-	sd_parse_cid(cid, resp);
-	if (verbose)
-		mmc_dump_cid(cid);
-
-	/* Get RCA of the card that responded */
-	ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR);
-	if (ret)
-		return ret;
-
-	mmc_rca = resp[0] >> 16;
-	if (verbose)
-		printf("SD Card detected (RCA %u)\n", mmc_rca);
-	mmc_card_is_sd = 1;
-	return 0;
-}
-
-static int mmc_init_card(struct mmc_cid *cid, int verbose)
-{
-	unsigned long resp[4];
-	int i, ret = 0;
-
-	mmc_idle_cards();
-	for (i = 0; i < 1000; i++) {
-		ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp,
-			      R3 | NID | OPEN_DRAIN);
-		if (ret || (resp[0] & 0x80000000))
-			break;
-		ret = -ETIMEDOUT;
-	}
-
-	if (ret)
-		return ret;
-
-	/* Get CID of all cards. FIXME: Support more than one card */
-	ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN);
-	if (ret)
-		return ret;
-	mmc_parse_cid(cid, resp);
-	if (verbose)
-		mmc_dump_cid(cid);
-
-	/* Set Relative Address of the card that responded */
-	ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp,
-		      R1 | NCR | OPEN_DRAIN);
-	return ret;
-}
-
-static void mci_set_data_timeout(struct mmc_csd *csd)
-{
-	static const unsigned int dtomul_to_shift[] = {
-		0, 4, 7, 8, 10, 12, 16, 20,
-	};
-	static const unsigned int taac_exp[] = {
-		1, 10, 100, 1000, 10000, 100000, 1000000, 10000000,
-	};
-	static const unsigned int taac_mant[] = {
-		0,  10, 12, 13, 15, 60, 25, 30,
-		35, 40, 45, 50, 55, 60, 70, 80,
-	};
-	unsigned int timeout_ns, timeout_clks;
-	unsigned int e, m;
-	unsigned int dtocyc, dtomul;
-	unsigned int shift;
-	u32 dtor;
-
-	e = csd->taac & 0x07;
-	m = (csd->taac >> 3) & 0x0f;
-
-	timeout_ns = (taac_exp[e] * taac_mant[m] + 9) / 10;
-	timeout_clks = csd->nsac * 100;
-
-	timeout_clks += (((timeout_ns + 9) / 10)
-			 * ((CFG_MMC_CLK_PP + 99999) / 100000) + 9999) / 10000;
-	if (!mmc_card_is_sd)
-		timeout_clks *= 10;
-	else
-		timeout_clks *= 100;
-
-	dtocyc = timeout_clks;
-	dtomul = 0;
-	while (dtocyc > 15 && dtomul < 8) {
-		dtomul++;
-		shift = dtomul_to_shift[dtomul];
-		dtocyc = (timeout_clks + (1 << shift) - 1) >> shift;
-	}
-
-	if (dtomul >= 8) {
-		dtomul = 7;
-		dtocyc = 15;
-		puts("Warning: Using maximum data timeout\n");
-	}
-
-	dtor = (MMCI_BF(DTOMUL, dtomul)
-		| MMCI_BF(DTOCYC, dtocyc));
-	mmci_writel(DTOR, dtor);
-
-	printf("mmc: Using %u cycles data timeout (DTOR=0x%x)\n",
-	       dtocyc << shift, dtor);
-}
-
-int mmc_init(int verbose)
-{
-	struct mmc_cid cid;
-	struct mmc_csd csd;
-	unsigned int max_blksz;
-	int ret;
-
-	/* Initialize controller */
-	mmci_writel(CR, MMCI_BIT(SWRST));
-	mmci_writel(CR, MMCI_BIT(MCIEN));
-	mmci_writel(DTOR, 0x5f);
-	mmci_writel(IDR, ~0UL);
-	mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
-
-	mmc_card_is_sd = 0;
-
-	ret = sd_init_card(&cid, verbose);
-	if (ret) {
-		mmc_rca = MMC_DEFAULT_RCA;
-		ret = mmc_init_card(&cid, verbose);
-	}
-	if (ret)
-		return ret;
-
-	/* Get CSD from the card */
-	ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, &csd, R2 | NCR);
-	if (ret)
-		return ret;
-	if (verbose)
-		mmc_dump_csd(&csd);
-
-	mci_set_data_timeout(&csd);
-
-	/* Initialize the blockdev structure */
-	mmc_blkdev.if_type = IF_TYPE_MMC;
-	mmc_blkdev.part_type = PART_TYPE_DOS;
-	mmc_blkdev.block_read = mmc_bread;
-	sprintf((char *)mmc_blkdev.vendor,
-		"Man %02x%04x Snr %08x",
-		cid.mid, cid.oid, cid.psn);
-	strncpy((char *)mmc_blkdev.product, cid.pnm,
-		sizeof(mmc_blkdev.product));
-	sprintf((char *)mmc_blkdev.revision, "%x %x",
-		cid.prv >> 4, cid.prv & 0x0f);
-
-	/*
-	 * If we can't use 512 byte blocks, refuse to deal with the
-	 * card. Tons of code elsewhere seems to depend on this.
-	 */
-	max_blksz = 1 << csd.read_bl_len;
-	if (max_blksz < 512 || (max_blksz > 512 && !csd.read_bl_partial)) {
-		printf("Card does not support 512 byte reads, aborting.\n");
-		return -ENODEV;
-	}
-	mmc_blkdev.blksz = 512;
-	mmc_blkdev.lba = (csd.c_size + 1) * (1 << (csd.c_size_mult + 2));
-
-	mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz);
-
-#if 0
-	if (fat_register_device(&mmc_blkdev, 1))
-		printf("Could not register MMC fat device\n");
-#else
-	init_part(&mmc_blkdev);
-#endif
-
-	return 0;
-}
-
-int mmc_read(ulong src, uchar *dst, int size)
-{
-	return -ENOSYS;
-}
-
-int mmc_write(uchar *src, ulong dst, int size)
-{
-	return -ENOSYS;
-}
-
-int mmc2info(ulong addr)
-{
-	return 0;
-}
-
-#endif /* CONFIG_MMC */
diff --git a/cpu/at32ap/atmel_mci.h b/cpu/at32ap/atmel_mci.h
deleted file mode 100644
index 5b4f5c9..0000000
--- a/cpu/at32ap/atmel_mci.h
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#ifndef __CPU_AT32AP_ATMEL_MCI_H__
-#define __CPU_AT32AP_ATMEL_MCI_H__
-
-/* Atmel MultiMedia Card Interface (MCI) registers */
-#define MMCI_CR					0x0000
-#define MMCI_MR					0x0004
-#define MMCI_DTOR				0x0008
-#define MMCI_SDCR				0x000c
-#define MMCI_ARGR				0x0010
-#define MMCI_CMDR				0x0014
-#define MMCI_RSPR				0x0020
-#define MMCI_RSPR1				0x0024
-#define MMCI_RSPR2				0x0028
-#define MMCI_RSPR3				0x002c
-#define MMCI_RDR				0x0030
-#define MMCI_TDR				0x0034
-#define MMCI_SR					0x0040
-#define MMCI_IER				0x0044
-#define MMCI_IDR				0x0048
-#define MMCI_IMR				0x004c
-
-/* Bitfields in CR */
-#define MMCI_MCIEN_OFFSET			0
-#define MMCI_MCIEN_SIZE				1
-#define MMCI_MCIDIS_OFFSET			1
-#define MMCI_MCIDIS_SIZE			1
-#define MMCI_PWSEN_OFFSET			2
-#define MMCI_PWSEN_SIZE				1
-#define MMCI_PWSDIS_OFFSET			3
-#define MMCI_PWSDIS_SIZE			1
-#define MMCI_SWRST_OFFSET			7
-#define MMCI_SWRST_SIZE				1
-
-/* Bitfields in MR */
-#define MMCI_CLKDIV_OFFSET			0
-#define MMCI_CLKDIV_SIZE			8
-#define MMCI_PWSDIV_OFFSET			8
-#define MMCI_PWSDIV_SIZE			3
-#define MMCI_RDPROOF_OFFSET			11
-#define MMCI_RDPROOF_SIZE			1
-#define MMCI_WRPROOF_OFFSET			12
-#define MMCI_WRPROOF_SIZE			1
-#define MMCI_PDCPADV_OFFSET			14
-#define MMCI_PDCPADV_SIZE			1
-#define MMCI_PDCMODE_OFFSET			15
-#define MMCI_PDCMODE_SIZE			1
-#define MMCI_BLKLEN_OFFSET			16
-#define MMCI_BLKLEN_SIZE			16
-
-/* Bitfields in DTOR */
-#define MMCI_DTOCYC_OFFSET			0
-#define MMCI_DTOCYC_SIZE			4
-#define MMCI_DTOMUL_OFFSET			4
-#define MMCI_DTOMUL_SIZE			3
-
-/* Bitfields in SDCR */
-#define MMCI_SCDSEL_OFFSET			0
-#define MMCI_SCDSEL_SIZE			4
-#define MMCI_SCDBUS_OFFSET			7
-#define MMCI_SCDBUS_SIZE			1
-
-/* Bitfields in ARGR */
-#define MMCI_ARG_OFFSET				0
-#define MMCI_ARG_SIZE				32
-
-/* Bitfields in CMDR */
-#define MMCI_CMDNB_OFFSET			0
-#define MMCI_CMDNB_SIZE				6
-#define MMCI_RSPTYP_OFFSET			6
-#define MMCI_RSPTYP_SIZE			2
-#define MMCI_SPCMD_OFFSET			8
-#define MMCI_SPCMD_SIZE				3
-#define MMCI_OPDCMD_OFFSET			11
-#define MMCI_OPDCMD_SIZE			1
-#define MMCI_MAXLAT_OFFSET			12
-#define MMCI_MAXLAT_SIZE			1
-#define MMCI_TRCMD_OFFSET			16
-#define MMCI_TRCMD_SIZE				2
-#define MMCI_TRDIR_OFFSET			18
-#define MMCI_TRDIR_SIZE				1
-#define MMCI_TRTYP_OFFSET			19
-#define MMCI_TRTYP_SIZE				2
-
-/* Bitfields in RSPRx */
-#define MMCI_RSP_OFFSET				0
-#define MMCI_RSP_SIZE				32
-
-/* Bitfields in SR/IER/IDR/IMR */
-#define MMCI_CMDRDY_OFFSET			0
-#define MMCI_CMDRDY_SIZE			1
-#define MMCI_RXRDY_OFFSET			1
-#define MMCI_RXRDY_SIZE				1
-#define MMCI_TXRDY_OFFSET			2
-#define MMCI_TXRDY_SIZE				1
-#define MMCI_BLKE_OFFSET			3
-#define MMCI_BLKE_SIZE				1
-#define MMCI_DTIP_OFFSET			4
-#define MMCI_DTIP_SIZE				1
-#define MMCI_NOTBUSY_OFFSET			5
-#define MMCI_NOTBUSY_SIZE			1
-#define MMCI_ENDRX_OFFSET			6
-#define MMCI_ENDRX_SIZE				1
-#define MMCI_ENDTX_OFFSET			7
-#define MMCI_ENDTX_SIZE				1
-#define MMCI_RXBUFF_OFFSET			14
-#define MMCI_RXBUFF_SIZE			1
-#define MMCI_TXBUFE_OFFSET			15
-#define MMCI_TXBUFE_SIZE			1
-#define MMCI_RINDE_OFFSET			16
-#define MMCI_RINDE_SIZE				1
-#define MMCI_RDIRE_OFFSET			17
-#define MMCI_RDIRE_SIZE				1
-#define MMCI_RCRCE_OFFSET			18
-#define MMCI_RCRCE_SIZE				1
-#define MMCI_RENDE_OFFSET			19
-#define MMCI_RENDE_SIZE				1
-#define MMCI_RTOE_OFFSET			20
-#define MMCI_RTOE_SIZE				1
-#define MMCI_DCRCE_OFFSET			21
-#define MMCI_DCRCE_SIZE				1
-#define MMCI_DTOE_OFFSET			22
-#define MMCI_DTOE_SIZE				1
-#define MMCI_OVRE_OFFSET			30
-#define MMCI_OVRE_SIZE				1
-#define MMCI_UNRE_OFFSET			31
-#define MMCI_UNRE_SIZE				1
-
-/* Constants for DTOMUL */
-#define MMCI_DTOMUL_1_CYCLE			0
-#define MMCI_DTOMUL_16_CYCLES			1
-#define MMCI_DTOMUL_128_CYCLES			2
-#define MMCI_DTOMUL_256_CYCLES			3
-#define MMCI_DTOMUL_1024_CYCLES			4
-#define MMCI_DTOMUL_4096_CYCLES			5
-#define MMCI_DTOMUL_65536_CYCLES		6
-#define MMCI_DTOMUL_1048576_CYCLES		7
-
-/* Constants for RSPTYP */
-#define MMCI_RSPTYP_NO_RESP			0
-#define MMCI_RSPTYP_48_BIT_RESP			1
-#define MMCI_RSPTYP_136_BIT_RESP		2
-
-/* Constants for SPCMD */
-#define MMCI_SPCMD_NO_SPEC_CMD			0
-#define MMCI_SPCMD_INIT_CMD			1
-#define MMCI_SPCMD_SYNC_CMD			2
-#define MMCI_SPCMD_INT_CMD			4
-#define MMCI_SPCMD_INT_RESP			5
-
-/* Constants for TRCMD */
-#define MMCI_TRCMD_NO_TRANS			0
-#define MMCI_TRCMD_START_TRANS			1
-#define MMCI_TRCMD_STOP_TRANS			2
-
-/* Constants for TRTYP */
-#define MMCI_TRTYP_BLOCK			0
-#define MMCI_TRTYP_MULTI_BLOCK			1
-#define MMCI_TRTYP_STREAM			2
-
-/* Bit manipulation macros */
-#define MMCI_BIT(name)					\
-	(1 << MMCI_##name##_OFFSET)
-#define MMCI_BF(name,value)				\
-	(((value) & ((1 << MMCI_##name##_SIZE) - 1))	\
-	 << MMCI_##name##_OFFSET)
-#define MMCI_BFEXT(name,value)				\
-	(((value) >> MMCI_##name##_OFFSET)\
-	 & ((1 << MMCI_##name##_SIZE) - 1))
-#define MMCI_BFINS(name,value,old)			\
-	(((old) & ~(((1 << MMCI_##name##_SIZE) - 1)	\
-		    << MMCI_##name##_OFFSET))		\
-	 | MMCI_BF(name,value))
-
-/* Register access macros */
-#define mmci_readl(reg)					\
-	readl((void *)MMCI_BASE + MMCI_##reg)
-#define mmci_writel(reg,value)				\
-	writel((value), (void *)MMCI_BASE + MMCI_##reg)
-
-#endif /* __CPU_AT32AP_ATMEL_MCI_H__ */
diff --git a/cpu/at32ap/cpu.c b/cpu/at32ap/cpu.c
index 311466b..0ba8361 100644
--- a/cpu/at32ap/cpu.c
+++ b/cpu/at32ap/cpu.c
@@ -30,7 +30,6 @@
 #include <asm/arch/memory-map.h>
 
 #include "hsmc3.h"
-#include "sm.h"
 
 /* Sanity checks */
 #if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB)		\
@@ -44,47 +43,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void pm_init(void)
-{
-	uint32_t cksel;
-
-#ifdef CONFIG_PLL
-	/* Initialize the PLL */
-	sm_writel(PM_PLL0, (SM_BF(PLLCOUNT, CFG_PLL0_SUPPRESS_CYCLES)
-			    | SM_BF(PLLMUL, CFG_PLL0_MUL - 1)
-			    | SM_BF(PLLDIV, CFG_PLL0_DIV - 1)
-			    | SM_BF(PLLOPT, CFG_PLL0_OPT)
-			    | SM_BF(PLLOSC, 0)
-			    | SM_BIT(PLLEN)));
-
-	/* Wait for lock */
-	while (!(sm_readl(PM_ISR) & SM_BIT(LOCK0))) ;
-#endif
-
-	/* Set up clocks for the CPU and all peripheral buses */
-	cksel = 0;
-	if (CFG_CLKDIV_CPU)
-		cksel |= SM_BIT(CPUDIV) | SM_BF(CPUSEL, CFG_CLKDIV_CPU - 1);
-	if (CFG_CLKDIV_HSB)
-		cksel |= SM_BIT(HSBDIV) | SM_BF(HSBSEL, CFG_CLKDIV_HSB - 1);
-	if (CFG_CLKDIV_PBA)
-		cksel |= SM_BIT(PBADIV) | SM_BF(PBASEL, CFG_CLKDIV_PBA - 1);
-	if (CFG_CLKDIV_PBB)
-		cksel |= SM_BIT(PBBDIV) | SM_BF(PBBSEL, CFG_CLKDIV_PBB - 1);
-	sm_writel(PM_CKSEL, cksel);
-
-	gd->cpu_hz = get_cpu_clk_rate();
-
-#ifdef CONFIG_PLL
-	/* Use PLL0 as main clock */
-	sm_writel(PM_MCCTRL, SM_BIT(PLLSEL));
-#endif
-}
-
 int cpu_init(void)
 {
 	extern void _evba(void);
-	char *p;
 
 	gd->cpu_hz = CFG_OSC0_HZ;
 
@@ -95,16 +56,15 @@ int cpu_init(void)
 	hsmc3_writel(PULSE0, 0x0b0a0906);
 	hsmc3_writel(SETUP0, 0x00010002);
 
-	pm_init();
+	clk_init();
 
+	/* Update the CPU speed according to the PLL configuration */
+	gd->cpu_hz = get_cpu_clk_rate();
+
+	/* Set up the exception handler table and enable exceptions */
 	sysreg_write(EVBA, (unsigned long)&_evba);
 	asm volatile("csrf	%0" : : "i"(SYSREG_EM_OFFSET));
 
-	/* Lock everything that mess with the flash in the icache */
-	for (p = __flashprog_start; p <= (__flashprog_end + CFG_ICACHE_LINESZ);
-	     p += CFG_ICACHE_LINESZ)
-		asm volatile("cache %0, 0x02" : "=m"(*p) :: "memory");
-
 	return 0;
 }
 
diff --git a/cpu/at32ap/entry.S b/cpu/at32ap/entry.S
deleted file mode 100644
index a6fc688..0000000
--- a/cpu/at32ap/entry.S
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <asm/sysreg.h>
-#include <asm/ptrace.h>
-
-	.section .text.exception,"ax"
-	.global	_evba
-	.type	_evba,@function
-	.align	10
-_evba:
-	.irp	x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
-	.align	2
-	rjmp	unknown_exception
-	.endr
-
-	.global	timer_interrupt_handler
-	.type	timer_interrupt_handler,@function
-	.align	2
-timer_interrupt_handler:
-	/*
-	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
-	 *
-	 * We're running at interrupt level 3, so we don't need to save
-	 * r8-r12 or lr to the stack.
-	 */
-	lda.w	r8, timer_overflow
-	ld.w	r9, r8[0]
-	mov	r10, -1
-	mtsr	SYSREG_COMPARE, r10
-	sub	r9, -1
-	st.w	r8[0], r9
-	rete
-
-	.type	unknown_exception, @function
-unknown_exception:
-	pushm	r0-r12
-	sub	r8, sp, REG_R12 - REG_R0 - 4
-	mov	r9, lr
-	mfsr	r10, SYSREG_RAR_EX
-	mfsr	r11, SYSREG_RSR_EX
-	pushm	r8-r11
-	mfsr	r12, SYSREG_ECR
-	mov	r11, sp
-	rcall	do_unknown_exception
-1:	rjmp	1b
diff --git a/cpu/at32ap/exception.c b/cpu/at32ap/exception.c
index 0672685..dc9c300 100644
--- a/cpu/at32ap/exception.c
+++ b/cpu/at32ap/exception.c
@@ -111,7 +111,8 @@ void do_unknown_exception(unsigned int ecr, struct pt_regs *regs)
 	printf("CPU Mode: %s\n", cpu_modes[mode]);
 
 	/* Avoid exception loops */
-	if (regs->sp < CFG_SDRAM_BASE || regs->sp >= gd->stack_end)
+	if (regs->sp < (gd->stack_end - CONFIG_STACKSIZE)
+			|| regs->sp >= gd->stack_end)
 		printf("\nStack pointer seems bogus, won't do stack dump\n");
 	else
 		dump_mem("\nStack: ", regs->sp, gd->stack_end);
diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c
index 1fcfe75..992612b 100644
--- a/cpu/at32ap/hsdramc.c
+++ b/cpu/at32ap/hsdramc.c
@@ -30,39 +30,32 @@
 
 #include "hsdramc1.h"
 
-unsigned long sdram_init(const struct sdram_info *info)
+unsigned long sdram_init(void *sdram_base, const struct sdram_config *config)
 {
-	unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
 	unsigned long sdram_size;
-	unsigned long tmp;
-	unsigned long bus_hz;
+	uint32_t cfgreg;
 	unsigned int i;
 
-	if (!info->refresh_period)
-		panic("ERROR: SDRAM refresh period == 0. "
-				"Please update the board code\n");
-
-	tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
-	       | HSDRAMC1_BF(NR, info->row_bits - 11)
-	       | HSDRAMC1_BF(NB, info->bank_bits - 1)
-	       | HSDRAMC1_BF(CAS, info->cas)
-	       | HSDRAMC1_BF(TWR, info->twr)
-	       | HSDRAMC1_BF(TRC, info->trc)
-	       | HSDRAMC1_BF(TRP, info->trp)
-	       | HSDRAMC1_BF(TRCD, info->trcd)
-	       | HSDRAMC1_BF(TRAS, info->tras)
-	       | HSDRAMC1_BF(TXSR, info->txsr));
-
-#ifdef CFG_SDRAM_16BIT
-	tmp |= HSDRAMC1_BIT(DBW);
-	sdram_size = 1 << (info->row_bits + info->col_bits
-			   + info->bank_bits + 1);
-#else
-	sdram_size = 1 << (info->row_bits + info->col_bits
-			   + info->bank_bits + 2);
-#endif
-
-	hsdramc1_writel(CR, tmp);
+	cfgreg = (HSDRAMC1_BF(NC, config->col_bits - 8)
+		       | HSDRAMC1_BF(NR, config->row_bits - 11)
+		       | HSDRAMC1_BF(NB, config->bank_bits - 1)
+		       | HSDRAMC1_BF(CAS, config->cas)
+		       | HSDRAMC1_BF(TWR, config->twr)
+		       | HSDRAMC1_BF(TRC, config->trc)
+		       | HSDRAMC1_BF(TRP, config->trp)
+		       | HSDRAMC1_BF(TRCD, config->trcd)
+		       | HSDRAMC1_BF(TRAS, config->tras)
+		       | HSDRAMC1_BF(TXSR, config->txsr));
+
+	if (config->data_bits == SDRAM_DATA_16BIT)
+		cfgreg |= HSDRAMC1_BIT(DBW);
+
+	hsdramc1_writel(CR, cfgreg);
+
+	/* Send a NOP to turn on the clock (necessary on some chips) */
+	hsdramc1_writel(MR, HSDRAMC1_MODE_NOP);
+	hsdramc1_readl(MR);
+	writel(0, sdram_base);
 
 	/*
 	 * Initialization sequence for SDRAM, from the data sheet:
@@ -77,7 +70,7 @@ unsigned long sdram_init(const struct sdram_info *info)
 	 */
 	hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
 	hsdramc1_readl(MR);
-	writel(0, sdram);
+	writel(0, sdram_base);
 
 	/*
 	 * 3. Eight auto-refresh (CBR) cycles are provided
@@ -85,58 +78,41 @@ unsigned long sdram_init(const struct sdram_info *info)
 	hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
 	hsdramc1_readl(MR);
 	for (i = 0; i < 8; i++)
-		writel(0, sdram);
+		writel(0, sdram_base);
 
 	/*
 	 * 4. A mode register set (MRS) cycle is issued to program
 	 *    SDRAM parameters, in particular CAS latency and burst
 	 *    length.
 	 *
-	 * CAS from info struct, burst length 1, serial burst type
+	 * The address will be chosen by the SDRAMC automatically; we
+	 * just have to make sure BA[1:0] are set to 0.
 	 */
 	hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
 	hsdramc1_readl(MR);
-	writel(0, sdram + (info->cas << 4));
+	writel(0, sdram_base);
 
 	/*
-	 * 5. A Normal Mode command is provided, 3 clocks after tMRD
-	 *    is met.
-	 *
-	 * From the timing diagram, it looks like tMRD is 3
-	 * cycles...try a dummy read from the peripheral bus.
+	 * 5. The application must go into Normal Mode, setting Mode
+	 *    to 0 in the Mode Register and performing a write access
+	 *    at any location in the SDRAM.
 	 */
-	hsdramc1_readl(MR);
 	hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
 	hsdramc1_readl(MR);
-	writel(0, sdram);
+	writel(0, sdram_base);
 
 	/*
 	 * 6. Write refresh rate into SDRAMC refresh timer count
 	 *    register (refresh rate = timing between refresh cycles).
-	 *
-	 * 15.6 us is a typical value for a burst of length one
 	 */
-	bus_hz = get_sdram_clk_rate();
-	hsdramc1_writel(TR, info->refresh_period);
-
-	printf("SDRAM: %u MB at address 0x%08lx\n",
-	       sdram_size >> 20, info->phys_addr);
-
-	printf("Testing SDRAM...");
-	for (i = 0; i < sdram_size / 4; i++)
-		sdram[i] = i;
-
-	for (i = 0; i < sdram_size / 4; i++) {
-		tmp = sdram[i];
-		if (tmp != i) {
-			printf("FAILED at address 0x%08lx\n",
-			       info->phys_addr + i * 4);
-			printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
-			return 0;
-		}
-	}
-
-	puts("OK\n");
+	hsdramc1_writel(TR, config->refresh_period);
+
+	if (config->data_bits == SDRAM_DATA_16BIT)
+		sdram_size = 1 << (config->row_bits + config->col_bits
+				   + config->bank_bits + 1);
+	else
+		sdram_size = 1 << (config->row_bits + config->col_bits
+				   + config->bank_bits + 2);
 
 	return sdram_size;
 }
diff --git a/cpu/at32ap/interrupts.c b/cpu/at32ap/interrupts.c
index bef1f30..160838e 100644
--- a/cpu/at32ap/interrupts.c
+++ b/cpu/at32ap/interrupts.c
@@ -98,18 +98,16 @@ void set_timer(unsigned long t)
  */
 void udelay(unsigned long usec)
 {
-	unsigned long now, end;
+	unsigned long cycles;
+	unsigned long base;
+	unsigned long now;
 
-	now = sysreg_read(COUNT);
+	base = sysreg_read(COUNT);
+	cycles = ((usec * (get_tbclk() / 10000)) + 50) / 100;
 
-	end = ((usec * (get_tbclk() / 10000)) + 50) / 100;
-	end += now;
-
-	while (now > end)
-		now = sysreg_read(COUNT);
-
-	while (now < end)
+	do {
 		now = sysreg_read(COUNT);
+	} while ((now - base) < cycles);
 }
 
 static int set_interrupt_handler(unsigned int nr, void (*handler)(void),
diff --git a/cpu/at32ap/pio.c b/cpu/at32ap/pio.c
index 9ba0b8e..f64004b 100644
--- a/cpu/at32ap/pio.c
+++ b/cpu/at32ap/pio.c
@@ -58,3 +58,59 @@ void gpio_select_periph_B(unsigned int pin, int use_pullup)
 	else
 		pio2_writel(base, PUDR, mask);
 }
+
+void gpio_select_pio(unsigned int pin, unsigned long gpiof_flags)
+{
+	void *base = gpio_pin_to_addr(pin);
+	uint32_t mask = 1 << (pin & 0x1f);
+
+	if (!base)
+		panic("Invalid GPIO pin %u\n", pin);
+
+	if (gpiof_flags & GPIOF_OUTPUT) {
+		if (gpiof_flags & GPIOF_MULTIDRV)
+			pio2_writel(base, MDER, mask);
+		else
+			pio2_writel(base, MDDR, mask);
+		pio2_writel(base, PUDR, mask);
+		pio2_writel(base, OER, mask);
+	} else {
+		if (gpiof_flags & GPIOF_PULLUP)
+			pio2_writel(base, PUER, mask);
+		else
+			pio2_writel(base, PUDR, mask);
+		if (gpiof_flags & GPIOF_DEGLITCH)
+			pio2_writel(base, IFER, mask);
+		else
+			pio2_writel(base, IFDR, mask);
+		pio2_writel(base, ODR, mask);
+	}
+
+	pio2_writel(base, PER, mask);
+}
+
+void gpio_set_value(unsigned int pin, int value)
+{
+	void *base = gpio_pin_to_addr(pin);
+	uint32_t mask = 1 << (pin & 0x1f);
+
+	if (!base)
+		panic("Invalid GPIO pin %u\n", pin);
+
+	if (value)
+		pio2_writel(base, SODR, mask);
+	else
+		pio2_writel(base, CODR, mask);
+}
+
+int gpio_get_value(unsigned int pin)
+{
+	void *base = gpio_pin_to_addr(pin);
+	int value;
+
+	if (!base)
+		panic("Invalid GPIO pin %u\n", pin);
+
+	value = pio2_readl(base, PDSR);
+	return (value >> (pin & 0x1f)) & 1;
+}
diff --git a/cpu/at32ap/pm.c b/cpu/at32ap/pm.c
deleted file mode 100644
index c78d547..0000000
--- a/cpu/at32ap/pm.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-
-#ifdef CFG_POWER_MANAGER
-#include <asm/errno.h>
-#include <asm/io.h>
-
-#include <asm/arch/memory-map.h>
-
-#include "sm.h"
-
-
-#ifdef CONFIG_PLL
-#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL)
-#else
-#define MAIN_CLK_RATE (CFG_OSC0_HZ)
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-
-#endif /* CFG_POWER_MANAGER */
diff --git a/cpu/at32ap/start.S b/cpu/at32ap/start.S
index ab8c2b7..907e9b1 100644
--- a/cpu/at32ap/start.S
+++ b/cpu/at32ap/start.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2005-2006 Atmel Corporation
+ * Copyright (C) 2005-2008 Atmel Corporation
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -20,12 +20,9 @@
  * MA 02111-1307 USA
  */
 #include <config.h>
+#include <asm/ptrace.h>
 #include <asm/sysreg.h>
 
-#ifndef PART_SPECIFIC_BOOTSTRAP
-# define PART_SPECIFIC_BOOTSTRAP
-#endif
-
 #define SYSREG_MMUCR_I_OFFSET	2
 #define SYSREG_MMUCR_S_OFFSET	4
 
@@ -34,11 +31,115 @@
 		    | SYSREG_BIT(FE) | SYSREG_BIT(RE)		\
 		    | SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
 
-	.text
+	/*
+	 * To save some space, we use the same entry point for
+	 * exceptions and reset. This avoids lots of alignment padding
+	 * since the reset vector is always suitably aligned.
+	 */
+	.section .exception.text, "ax", @progbits
 	.global	_start
+	.global	_evba
+	.type	_start, @function
+	.type	_evba, @function
 _start:
-	PART_SPECIFIC_BOOTSTRAP
+	.size	_start, 0
+_evba:
+	.org	0x00
+	rjmp	unknown_exception	/* Unrecoverable exception */
+	.org	0x04
+	rjmp	unknown_exception	/* TLB multiple hit */
+	.org	0x08
+	rjmp	unknown_exception	/* Bus error data fetch */
+	.org	0x0c
+	rjmp	unknown_exception	/* Bus error instruction fetch */
+	.org	0x10
+	rjmp	unknown_exception	/* NMI */
+	.org	0x14
+	rjmp	unknown_exception	/* Instruction address */
+	.org	0x18
+	rjmp	unknown_exception	/* ITLB protection */
+	.org	0x1c
+	rjmp	unknown_exception	/* Breakpoint */
+	.org	0x20
+	rjmp	unknown_exception	/* Illegal opcode */
+	.org	0x24
+	rjmp	unknown_exception	/* Unimplemented instruction */
+	.org	0x28
+	rjmp	unknown_exception	/* Privilege violation */
+	.org	0x2c
+	rjmp	unknown_exception	/* Floating-point */
+	.org	0x30
+	rjmp	unknown_exception	/* Coprocessor absent */
+	.org	0x34
+	rjmp	unknown_exception	/* Data Address (read) */
+	.org	0x38
+	rjmp	unknown_exception	/* Data Address (write) */
+	.org	0x3c
+	rjmp	unknown_exception	/* DTLB Protection (read) */
+	.org	0x40
+	rjmp	unknown_exception	/* DTLB Protection (write) */
+	.org	0x44
+	rjmp	unknown_exception	/* DTLB Modified */
+
+	.org	0x50
+	rjmp	unknown_exception	/* ITLB Miss */
+	.org	0x60
+	rjmp	unknown_exception	/* DTLB Miss (read) */
+	.org	0x70
+	rjmp	unknown_exception	/* DTLB Miss (write) */
+
+	.size	_evba, . - _evba
+
+	.align	2
+	.type	unknown_exception, @function
+unknown_exception:
+	/* Figure out whether we're handling an exception (Exception
+	 * mode) or just booting (Supervisor mode). */
+	csrfcz	SYSREG_M1_OFFSET
+	brcc	at32ap_cpu_bootstrap
+
+	/* This is an exception. Complain. */
+	pushm	r0-r12
+	sub	r8, sp, REG_R12 - REG_R0 - 4
+	mov	r9, lr
+	mfsr	r10, SYSREG_RAR_EX
+	mfsr	r11, SYSREG_RSR_EX
+	pushm	r8-r11
+	mfsr	r12, SYSREG_ECR
+	mov	r11, sp
+	rcall	do_unknown_exception
+1:	rjmp	1b
+
+	/* The COUNT/COMPARE timer interrupt handler */
+	.global	timer_interrupt_handler
+	.type	timer_interrupt_handler,@function
+	.align	2
+timer_interrupt_handler:
+	/*
+	 * Increment timer_overflow and re-write COMPARE with 0xffffffff.
+	 *
+	 * We're running at interrupt level 3, so we don't need to save
+	 * r8-r12 or lr to the stack.
+	 */
+	lda.w	r8, timer_overflow
+	ld.w	r9, r8[0]
+	mov	r10, -1
+	mtsr	SYSREG_COMPARE, r10
+	sub	r9, -1
+	st.w	r8[0], r9
+	rete
 
+	/*
+	 * CPU bootstrap after reset is handled here. SoC code may
+	 * override this in case they need to initialize oscillators,
+	 * etc.
+	 */
+	.section .text.at32ap_cpu_bootstrap, "ax", @progbits
+	.global	at32ap_cpu_bootstrap
+	.weak	at32ap_cpu_bootstrap
+	.type	at32ap_cpu_bootstrap, @function
+	.align	2
+at32ap_cpu_bootstrap:
 	/* Reset the Status Register */
 	mov	r0, lo(SR_INIT)
 	orh	r0, hi(SR_INIT)
@@ -66,9 +167,16 @@ _start:
 	lddpc	pc, 1f
 
 	.align	2
-1:	.long	2f
+1:	.long	at32ap_low_level_init
+	.size	_start, . - _start
 
-2:	lddpc	sp, sp_init
+	/* Common CPU bootstrap code after oscillator/cache/etc. init */
+	.section .text.avr32ap_low_level_init, "ax", @progbits
+	.global	at32ap_low_level_init
+	.type	at32ap_low_level_init, @function
+	.align	2
+at32ap_low_level_init:
+	lddpc	sp, sp_init
 
 	/* Initialize the GOT pointer */
 	lddpc	r6, got_init
@@ -90,6 +198,7 @@ got_init:
 	 * Relocate the u-boot image into RAM and continue from there.
 	 * Does not return.
 	 */
+	.section .text.relocate_code,"ax",@progbits
 	.global	relocate_code
 	.type	relocate_code,@function
 relocate_code:
@@ -162,3 +271,5 @@ in_ram:
 	.align	2
 got_init_reloc:
 	.long	3b - _GLOBAL_OFFSET_TABLE_
+
+	.size	relocate_code, . - relocate_code