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| author | Wolfgang Denk <wd@pollux.denx.de> | 2006-10-24 14:27:35 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@pollux.denx.de> | 2006-10-24 14:27:35 +0200 |
| commit | 72a087e04705c26cad982879ebd06b5281bf825a (patch) | |
| tree | 98f36d7e04f8a8e88f188e50e6a0f45fb9f285e8 /cpu/at32ap/pio2.h | |
| parent | 7b64fef33c66be648826c0ff9758298ef13d0604 (diff) | |
| download | u-boot-imx-72a087e04705c26cad982879ebd06b5281bf825a.zip u-boot-imx-72a087e04705c26cad982879ebd06b5281bf825a.tar.gz u-boot-imx-72a087e04705c26cad982879ebd06b5281bf825a.tar.bz2 | |
Add AT32AP CPU and AT32AP7000 SoC support
Patch by Haavard Skinnemoen, 06 Sep 2006
This patch adds support for the AT32AP CPU family and the AT32AP7000
chip, which is the first chip implementing the AVR32 architecture.
The AT32AP CPU core is a high-performance implementation featuring a
7-stage pipeline, separate instruction- and data caches, and a MMU.
For more information, please see the "AVR32 AP Technical Reference":
http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf
In addition to this, the AT32AP7000 chip comes with a large set of
integrated peripherals, many of which are shared with the AT91 series
of ARM-based microcontrollers from Atmel. Full data sheet is
available here:
http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
Diffstat (limited to 'cpu/at32ap/pio2.h')
| -rw-r--r-- | cpu/at32ap/pio2.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/cpu/at32ap/pio2.h b/cpu/at32ap/pio2.h new file mode 100644 index 0000000..6b79de3 --- /dev/null +++ b/cpu/at32ap/pio2.h @@ -0,0 +1,44 @@ +/* + * Register definitions for Parallel Input/Output Controller + */ +#ifndef __CPU_AT32AP_PIO2_H__ +#define __CPU_AT32AP_PIO2_H__ + +/* PIO2 register offsets */ +#define PIO2_PER 0x0000 +#define PIO2_PDR 0x0004 +#define PIO2_PSR 0x0008 +#define PIO2_OER 0x0010 +#define PIO2_ODR 0x0014 +#define PIO2_OSR 0x0018 +#define PIO2_IFER 0x0020 +#define PIO2_IFDR 0x0024 +#define PIO2_ISFR 0x0028 +#define PIO2_SODR 0x0030 +#define PIO2_CODR 0x0034 +#define PIO2_ODSR 0x0038 +#define PIO2_PDSR 0x003c +#define PIO2_IER 0x0040 +#define PIO2_IDR 0x0044 +#define PIO2_IMR 0x0048 +#define PIO2_ISR 0x004c +#define PIO2_MDER 0x0050 +#define PIO2_MDDR 0x0054 +#define PIO2_MDSR 0x0058 +#define PIO2_PUDR 0x0060 +#define PIO2_PUER 0x0064 +#define PIO2_PUSR 0x0068 +#define PIO2_ASR 0x0070 +#define PIO2_BSR 0x0074 +#define PIO2_ABSR 0x0078 +#define PIO2_OWER 0x00a0 +#define PIO2_OWDR 0x00a4 +#define PIO2_OWSR 0x00a8 + +/* Register access macros */ +#define pio2_readl(port,reg) \ + readl((port)->regs + PIO2_##reg) +#define pio2_writel(port,reg,value) \ + writel((value), (port)->regs + PIO2_##reg) + +#endif /* __CPU_AT32AP_PIO2_H__ */ |