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| author | Sanjeev Premi <premi@ti.com> | 2009-04-27 21:27:54 +0530 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-04-29 21:11:49 +0200 |
| commit | cba0b778dd5f1ea32959b6825c7f0a31501a99d5 (patch) | |
| tree | e669eb53350b92adef4aa44e4b1c262d74246ee1 /cpu/arm_cortexa8/omap3/clock.c | |
| parent | 90006e9b33bcdbf241b0295d186e3634137907a9 (diff) | |
| download | u-boot-imx-cba0b778dd5f1ea32959b6825c7f0a31501a99d5.zip u-boot-imx-cba0b778dd5f1ea32959b6825c7f0a31501a99d5.tar.gz u-boot-imx-cba0b778dd5f1ea32959b6825c7f0a31501a99d5.tar.bz2 | |
OMAP3: Print correct silicon revision
The function display_board_info() displays incorrect
silicon revision - based on the return value from
function get_cpu_rev().
This patch fixes the problem.
Signed-off-by: Sanjeev Premi <premi@ti.com>
Diffstat (limited to 'cpu/arm_cortexa8/omap3/clock.c')
| -rw-r--r-- | cpu/arm_cortexa8/omap3/clock.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/cpu/arm_cortexa8/omap3/clock.c b/cpu/arm_cortexa8/omap3/clock.c index 8ac31be..d035677 100644 --- a/cpu/arm_cortexa8/omap3/clock.c +++ b/cpu/arm_cortexa8/omap3/clock.c @@ -132,7 +132,7 @@ void prcm_init(void) void (*f_lock_pll) (u32, u32, u32, u32); int xip_safe, p0, p1, p2, p3; u32 osc_clk = 0, sys_clkin_sel; - u32 clk_index, sil_index; + u32 clk_index, sil_index = 0; prm_t *prm_base = (prm_t *)PRM_BASE; prcm_t *prcm_base = (prcm_t *)PRCM_BASE; dpll_param *dpll_param_p; @@ -170,7 +170,8 @@ void prcm_init(void) * and sil_index will get the values for that SysClk for the * appropriate silicon rev. */ - sil_index = get_cpu_rev() - 1; + if (get_cpu_rev()) + sil_index = 1; /* Unlock MPU DPLL (slows things down, and needed later) */ sr32(&prcm_base->clken_pll_mpu, 0, 3, PLL_LOW_POWER_BYPASS); |