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author | Wolfgang Denk <wd@denx.de> | 2009-07-07 22:22:05 +0200 |
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committer | Wolfgang Denk <wd@denx.de> | 2009-07-07 22:22:05 +0200 |
commit | a48ecc969f8d2d0fe9167962e9b8b4cca52de10b (patch) | |
tree | 604e04770713cb314cb6184e26eeb4319dec3d43 /cpu/arm_cortexa8/cpu.c | |
parent | bec9cab9291bb221714d559a44fe37669a8ca604 (diff) | |
parent | ceb70b466e75ceb1a621b6163f7e31116bfc8094 (diff) | |
download | u-boot-imx-a48ecc969f8d2d0fe9167962e9b8b4cca52de10b.zip u-boot-imx-a48ecc969f8d2d0fe9167962e9b8b4cca52de10b.tar.gz u-boot-imx-a48ecc969f8d2d0fe9167962e9b8b4cca52de10b.tar.bz2 |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts:
drivers/spi/Makefile
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'cpu/arm_cortexa8/cpu.c')
-rw-r--r-- | cpu/arm_cortexa8/cpu.c | 70 |
1 files changed, 4 insertions, 66 deletions
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 6fd07d0..fcb5775 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -33,12 +33,8 @@ #include <common.h> #include <command.h> -#include <asm/arch/sys_proto.h> #include <asm/system.h> - -#ifndef CONFIG_L2_OFF -void l2cache_disable(void); -#endif +#include <asm/cache.h> static void cache_flush(void); @@ -63,7 +59,7 @@ int cleanup_before_linux(void) #ifndef CONFIG_L2_OFF /* turn off L2 cache */ - l2cache_disable(); + l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif @@ -72,72 +68,14 @@ int cleanup_before_linux(void) asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); #ifndef CONFIG_L2_OFF - l2cache_enable(); + l2_cache_enable(); #endif return 0; } -void l2cache_enable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("orr r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } - -} - -void l2cache_disable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("bic r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } -} - static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } + |