summaryrefslogtreecommitdiff
path: root/cpu/arm926ejs
diff options
context:
space:
mode:
authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-04-05 13:06:31 +0200
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-04-05 13:06:31 +0200
commitb3acb6cd4059dfb29a5e99095d802717f53ff784 (patch)
tree0578103fde893d08e5b6127db4df18833ae3d075 /cpu/arm926ejs
parent677e62f43235de9a1701204d7bcea0fb3d233fa1 (diff)
downloadu-boot-imx-b3acb6cd4059dfb29a5e99095d802717f53ff784.zip
u-boot-imx-b3acb6cd4059dfb29a5e99095d802717f53ff784.tar.gz
u-boot-imx-b3acb6cd4059dfb29a5e99095d802717f53ff784.tar.bz2
arm: clean cache management
unify arm cache management except for non standard cache as ARM7TDMI Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/arm926ejs')
-rw-r--r--cpu/arm926ejs/cpu.c72
1 files changed, 10 insertions, 62 deletions
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index d1748c9..84c169e 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -38,13 +38,7 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
-static void cp_delay (void)
-{
- volatile int i;
-
- /* copro seems to need some delay between reading and writing */
- for (i = 0; i < 100; i++);
-}
+static void cache_flush(void);
int cpu_init (void)
{
@@ -67,20 +61,16 @@ int cleanup_before_linux (void)
* we turn off caches etc ...
*/
- unsigned long i;
-
disable_interrupts ();
- /* turn off I/D-cache */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(CR_C | CR_I);
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+ /* turn off I/D-cache */
+ icache_disable();
+ dcache_disable();
/* flush I/D-cache */
- i = 0;
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+ cache_flush();
- return (0);
+ return 0;
}
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -91,52 +81,10 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return (0);
}
-/* cache_bit must be either CR_I or CR_C */
-static void cache_enable(uint32_t cache_bit)
-{
- uint32_t reg;
-
- reg = get_cr(); /* get control reg. */
- cp_delay();
- set_cr(reg | cache_bit);
-}
-
-/* cache_bit must be either CR_I or CR_C */
-static void cache_disable(uint32_t cache_bit)
-{
- uint32_t reg;
-
- reg = get_cr();
- cp_delay();
- set_cr(reg & ~cache_bit);
-}
-
-void icache_enable(void)
-{
- cache_enable(CR_I);
-}
-
-void icache_disable(void)
-{
- cache_disable(CR_I);
-}
-
-int icache_status(void)
-{
- return (get_cr() & CR_I) != 0;
-}
-
-void dcache_enable(void)
-{
- cache_enable(CR_C);
-}
-
-void dcache_disable(void)
+/* flush I/D-cache */
+static void cache_flush (void)
{
- cache_disable(CR_C);
-}
+ unsigned long i = 0;
-int dcache_status(void)
-{
- return (get_cr() & CR_C) != 0;
+ asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
}