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| author | Gururaja Hebbar K R <gururajakr@sanyo.co.in> | 2008-08-25 11:11:34 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-08-25 13:00:03 +0200 |
| commit | e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6 (patch) | |
| tree | 5cc265595c6f75283f7e67e8d3a3ea5575afa868 /cpu/arm926ejs/versatile/timer.c | |
| parent | 535cfa4f3de86cf48d6c0af1daf33aebdca089f9 (diff) | |
| download | u-boot-imx-e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6.zip u-boot-imx-e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6.tar.gz u-boot-imx-e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6.tar.bz2 | |
Correct ARM Versatile Timer Initialization
- According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271),
-- Timer Value Register @ TIMER Base + 4 is Read-only.
-- Prescale Value (Bits 3-2 of TIMER Control register)
can only be one of 00,01,10. 11 is undefined.
-- CFG_HZ for Versatile board is set to
#define CFG_HZ (1000000 / 256)
So Prescale bits is set to indicate
- 8 Stages of Prescale, Clock divided by 256
- The Timer Control Register has one Undefined/Shouldn't Use Bit
So we should do read/modify/write Operation
Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
Diffstat (limited to 'cpu/arm926ejs/versatile/timer.c')
| -rwxr-xr-x[-rw-r--r--] | cpu/arm926ejs/versatile/timer.c | 39 |
1 files changed, 35 insertions, 4 deletions
diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c index 32872d2..f01f318 100644..100755 --- a/cpu/arm926ejs/versatile/timer.c +++ b/cpu/arm926ejs/versatile/timer.c @@ -46,12 +46,43 @@ static ulong timestamp; static ulong lastdec; -/* nothing really to do with interrupts, just starts up a counter. */ +#define TIMER_ENABLE (1 << 7) +#define TIMER_MODE_MSK (1 << 6) +#define TIMER_MODE_FR (0 << 6) +#define TIMER_MODE_PD (1 << 6) + +#define TIMER_INT_EN (1 << 5) +#define TIMER_PRS_MSK (3 << 2) +#define TIMER_PRS_8S (1 << 3) +#define TIMER_SIZE_MSK (1 << 2) +#define TIMER_ONE_SHT (1 << 0) + int timer_init (void) { - *(volatile ulong *)(CFG_TIMERBASE + 0) = CFG_TIMER_RELOAD; /* TimerLoad */ - *(volatile ulong *)(CFG_TIMERBASE + 4) = CFG_TIMER_RELOAD; /* TimerValue */ - *(volatile ulong *)(CFG_TIMERBASE + 8) = 0x8C; + ulong tmr_ctrl_val; + + /* 1st disable the Timer */ + tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8); + tmr_ctrl_val &= ~TIMER_ENABLE; + *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val; + + /* + * The Timer Control Register has one Undefined/Shouldn't Use Bit + * So we should do read/modify/write Operation + */ + + /* + * Timer Mode : Free Running + * Interrupt : Disabled + * Prescale : 8 Stage, Clk/256 + * Tmr Siz : 16 Bit Counter + * Tmr in Wrapping Mode + */ + tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8); + tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT ); + tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S); + + *(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val; /* init the timestamp and lastdec value */ reset_timer_masked(); |