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| author | Wolfgang Denk <wd@denx.de> | 2008-04-11 15:11:26 +0200 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-04-11 15:11:26 +0200 |
| commit | 950a392464e616b4590bc4501be46e2d7d162dea (patch) | |
| tree | e33be5df8d39072af358f9e1febad383714cccc7 /cpu/arm926ejs/davinci/nand.c | |
| parent | aeff6d503b6006573d5c6b04fc658a64bebee5fa (diff) | |
| download | u-boot-imx-950a392464e616b4590bc4501be46e2d7d162dea.zip u-boot-imx-950a392464e616b4590bc4501be46e2d7d162dea.tar.gz u-boot-imx-950a392464e616b4590bc4501be46e2d7d162dea.tar.bz2 | |
Revert merge of git://www.denx.de/git/u-boot-arm, commit 62479b18:
Reverting became necessary after it turned out that the patches in
the u-boot-arm repo were modified, and in some cases corrupted.
This reverts the following commits:
066bebd6353e33af3adefc3404560871699e9961
7a837b7310166ae8fc8b8d66d7ef01b60a80f9d6
c88ae20580b2b01487b4cdcc8b2a113f551aee36
a147e56f03871bba4f05058d5e04ce7deb010b04
d6674e0e2a6a1f033945f78838566210d3f28c95
8c8463cce44d849e37744749b32d38e1dfb12e50
c98b47ad24b2d91f41c09a3d62d7f70ad84f4b7d
8bf69d81782619187933a605f1a95ee1d069478d
8c16cb0d3b971f46fbe77c072664c0f2dcd4471d
a574a73852a527779234e73e17e7597fd8128882
1377b5583a48021d983e1fd565f7d40c89e84d63
1704dc20917b4f71e373e2c888497ee666d40380
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'cpu/arm926ejs/davinci/nand.c')
| -rw-r--r-- | cpu/arm926ejs/davinci/nand.c | 41 |
1 files changed, 36 insertions, 5 deletions
diff --git a/cpu/arm926ejs/davinci/nand.c b/cpu/arm926ejs/davinci/nand.c index 3257f83..127be9f 100644 --- a/cpu/arm926ejs/davinci/nand.c +++ b/cpu/arm926ejs/davinci/nand.c @@ -117,7 +117,7 @@ static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode) dummy = emif_addr->NANDF3ECC; dummy = emif_addr->NANDF4ECC; - emif_addr->NANDFCR |= (1 << (CFG_DAVINCI_NANDCE + 6)); + emif_addr->NANDFCR |= (1 << 8); } static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region) @@ -147,7 +147,7 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u n = (this->eccmode == NAND_ECC_HW12_2048) ? 4 : 1; - region = (CFG_DAVINCI_NANDCE - 1); + region = 1; while (n--) { tmp = nand_davinci_readecc(mtd, region); *ecc_code++ = tmp; @@ -311,9 +311,40 @@ static int nand_davinci_waitfunc(struct mtd_info *mtd, struct nand_chip *this, i static void nand_flash_init(void) { - /* All EMIF initialization is done in lowlevel_init.S - * and config values are in the board config files - */ + u_int32_t acfg1 = 0x3ffffffc; + u_int32_t acfg2 = 0x3ffffffc; + u_int32_t acfg3 = 0x3ffffffc; + u_int32_t acfg4 = 0x3ffffffc; + emifregs emif_regs; + + /*------------------------------------------------------------------* + * NAND FLASH CHIP TIMEOUT @ 459 MHz * + * * + * AEMIF.CLK freq = PLL1/6 = 459/6 = 76.5 MHz * + * AEMIF.CLK period = 1/76.5 MHz = 13.1 ns * + * * + *------------------------------------------------------------------*/ + acfg1 = 0 + | (0 << 31 ) /* selectStrobe */ + | (0 << 30 ) /* extWait */ + | (1 << 26 ) /* writeSetup 10 ns */ + | (3 << 20 ) /* writeStrobe 40 ns */ + | (1 << 17 ) /* writeHold 10 ns */ + | (1 << 13 ) /* readSetup 10 ns */ + | (5 << 7 ) /* readStrobe 60 ns */ + | (1 << 4 ) /* readHold 10 ns */ + | (3 << 2 ) /* turnAround ?? ns */ + | (0 << 0 ) /* asyncSize 8-bit bus */ + ; + + emif_regs = (emifregs)DAVINCI_ASYNC_EMIF_CNTRL_BASE; + + emif_regs->AWCCR |= 0x10000000; + emif_regs->AB1CR = acfg1; /* 0x08244128 */; + emif_regs->AB2CR = acfg2; + emif_regs->AB3CR = acfg3; + emif_regs->AB4CR = acfg4; + emif_regs->NANDFCR = 0x00000101; } int board_nand_init(struct nand_chip *nand) |