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author | Stefan Roese <sr@denx.de> | 2008-07-14 10:45:47 +0200 |
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committer | Stefan Roese <sr@denx.de> | 2008-07-14 10:45:47 +0200 |
commit | 4b326101d6cfaeab8250988bc4c7f51e6c92d719 (patch) | |
tree | d04632af08591263f5cd6fc8a5c6ba8ac3d6d246 /cpu/arm926ejs/cpu.c | |
parent | 69e2c6d0d13d7c8cf1612ac090bdc4c59ba6858e (diff) | |
parent | d5996dd555edf52721b7691a4c59de016251ed39 (diff) | |
download | u-boot-imx-4b326101d6cfaeab8250988bc4c7f51e6c92d719.zip u-boot-imx-4b326101d6cfaeab8250988bc4c7f51e6c92d719.tar.gz u-boot-imx-4b326101d6cfaeab8250988bc4c7f51e6c92d719.tar.bz2 |
Merge branch 'master' of /home/stefan/git/u-boot/u-boot into next
Diffstat (limited to 'cpu/arm926ejs/cpu.c')
-rw-r--r-- | cpu/arm926ejs/cpu.c | 51 |
1 files changed, 39 insertions, 12 deletions
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c index 722732e..56c6289 100644 --- a/cpu/arm926ejs/cpu.c +++ b/cpu/arm926ejs/cpu.c @@ -134,25 +134,52 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return (0); } -void icache_enable (void) +/* cache_bit must be either C1_IC or C1_DC */ +static void cache_enable(uint32_t cache_bit) { - ulong reg; + uint32_t reg; - reg = read_p15_c1 (); /* get control reg. */ - cp_delay (); - write_p15_c1 (reg | C1_IC); + reg = read_p15_c1(); /* get control reg. */ + cp_delay(); + write_p15_c1(reg | cache_bit); } -void icache_disable (void) +/* cache_bit must be either C1_IC or C1_DC */ +static void cache_disable(uint32_t cache_bit) { - ulong reg; + uint32_t reg; - reg = read_p15_c1 (); - cp_delay (); - write_p15_c1 (reg & ~C1_IC); + reg = read_p15_c1(); + cp_delay(); + write_p15_c1(reg & ~cache_bit); } -int icache_status (void) +void icache_enable(void) { - return (read_p15_c1 () & C1_IC) != 0; + cache_enable(C1_IC); +} + +void icache_disable(void) +{ + cache_disable(C1_IC); +} + +int icache_status(void) +{ + return (read_p15_c1() & C1_IC) != 0; +} + +void dcache_enable(void) +{ + cache_enable(C1_DC); +} + +void dcache_disable(void) +{ + cache_disable(C1_DC); +} + +int dcache_status(void) +{ + return (read_p15_c1() & C1_DC) != 0; } |