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authorHugo Villeneuve <hugo.villeneuve@lyrtech.com>2008-07-10 10:46:33 -0400
committerWolfgang Denk <wd@denx.de>2008-07-13 15:05:11 +0200
commitc15947d6ce0d59925c97fdfac692476af6e262d0 (patch)
treecf61af6158424678ae5cfe036dbbb32cb0962546 /cpu/arm926ejs/cpu.c
parent068c1b77c8f42a1a31084d2f4b1d5cc807c1a9ce (diff)
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ARM: Fix for broken compilation when defining CONFIG_CMD_ELF
caused by missing dcache status/enable/disable functions. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
Diffstat (limited to 'cpu/arm926ejs/cpu.c')
-rw-r--r--cpu/arm926ejs/cpu.c51
1 files changed, 39 insertions, 12 deletions
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 722732e..56c6289 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -134,25 +134,52 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return (0);
}
-void icache_enable (void)
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_enable(uint32_t cache_bit)
{
- ulong reg;
+ uint32_t reg;
- reg = read_p15_c1 (); /* get control reg. */
- cp_delay ();
- write_p15_c1 (reg | C1_IC);
+ reg = read_p15_c1(); /* get control reg. */
+ cp_delay();
+ write_p15_c1(reg | cache_bit);
}
-void icache_disable (void)
+/* cache_bit must be either C1_IC or C1_DC */
+static void cache_disable(uint32_t cache_bit)
{
- ulong reg;
+ uint32_t reg;
- reg = read_p15_c1 ();
- cp_delay ();
- write_p15_c1 (reg & ~C1_IC);
+ reg = read_p15_c1();
+ cp_delay();
+ write_p15_c1(reg & ~cache_bit);
}
-int icache_status (void)
+void icache_enable(void)
{
- return (read_p15_c1 () & C1_IC) != 0;
+ cache_enable(C1_IC);
+}
+
+void icache_disable(void)
+{
+ cache_disable(C1_IC);
+}
+
+int icache_status(void)
+{
+ return (read_p15_c1() & C1_IC) != 0;
+}
+
+void dcache_enable(void)
+{
+ cache_enable(C1_DC);
+}
+
+void dcache_disable(void)
+{
+ cache_disable(C1_DC);
+}
+
+int dcache_status(void)
+{
+ return (read_p15_c1() & C1_DC) != 0;
}