at91: Introduction of at91sam9g45 SOC.

AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz.
It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of
peripherals.

The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES.
On the board you can find 2 USART, USB high speed,
a 480*272 LG lcd, ethernet, gpio/joystick/buttons.

Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>

3 files changed, 187 insertions, 2 deletions

diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile
index 3da89f4..69051c1 100644
--- a/cpu/arm926ejs/at91/Makefile
+++ b/cpu/arm926ejs/at91/Makefile
@@ -31,6 +31,8 @@ COBJS-$(CONFIG_AT91SAM9G20)	+= at91sam9260_devices.o
 COBJS-$(CONFIG_AT91SAM9261)	+= at91sam9261_devices.o
 COBJS-$(CONFIG_AT91SAM9263)	+= at91sam9263_devices.o
 COBJS-$(CONFIG_AT91SAM9RL)	+= at91sam9rl_devices.o
+COBJS-$(CONFIG_AT91SAM9M10G45)	+= at91sam9m10g45_devices.o
+COBJS-$(CONFIG_AT91SAM9G45)	+= at91sam9m10g45_devices.o
 COBJS-$(CONFIG_AT91_LED)	+= led.o
 COBJS-y += clock.o
 COBJS-y += cpu.o
diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
new file mode 100644
index 0000000..98d90f2
--- /dev/null
+++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
@@ -0,0 +1,175 @@
+/*
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/io.h>
+
+void at91_serial0_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB19, 1);	/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PB18, 0);	/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0);
+}
+
+void at91_serial1_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD1 */
+	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD1 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1);
+}
+
+void at91_serial2_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PD6, 1);		/* TXD2 */
+	at91_set_A_periph(AT91_PIN_PD7, 0);		/* RXD2 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2);
+}
+
+void at91_serial3_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PB12, 0);	/* DRXD */
+	at91_set_A_periph(AT91_PIN_PB13, 1);	/* DTXD */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);;
+}
+
+void at91_serial_hw_init(void)
+{
+#ifdef CONFIG_USART0
+	at91_serial0_hw_init();
+#endif
+
+#ifdef CONFIG_USART1
+	at91_serial1_hw_init();
+#endif
+
+#ifdef CONFIG_USART2
+	at91_serial2_hw_init();
+#endif
+
+#ifdef CONFIG_USART3	/* DBGU */
+	at91_serial3_hw_init();
+#endif
+}
+
+#ifdef CONFIG_ATMEL_SPI
+void at91_spi0_hw_init(unsigned long cs_mask)
+{
+	at91_set_A_periph(AT91_PIN_PB0, 0);	/* SPI0_MISO */
+	at91_set_A_periph(AT91_PIN_PB1, 0);	/* SPI0_MOSI */
+	at91_set_A_periph(AT91_PIN_PB2, 0);	/* SPI0_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI0);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_A_periph(AT91_PIN_PB3, 0);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_B_periph(AT91_PIN_PB18, 0);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_B_periph(AT91_PIN_PB19, 0);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_B_periph(AT91_PIN_PD27, 0);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_gpio_output(AT91_PIN_PB3, 0);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_gpio_output(AT91_PIN_PB18, 0);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_gpio_output(AT91_PIN_PB19, 0);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_gpio_output(AT91_PIN_PD27, 0);
+	}
+}
+
+void at91_spi1_hw_init(unsigned long cs_mask)
+{
+	at91_set_A_periph(AT91_PIN_PB14, 0);	/* SPI1_MISO */
+	at91_set_A_periph(AT91_PIN_PB15, 0);	/* SPI1_MOSI */
+	at91_set_A_periph(AT91_PIN_PB16, 0);	/* SPI1_SPCK */
+
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_SPI1);
+
+	if (cs_mask & (1 << 0)) {
+		at91_set_A_periph(AT91_PIN_PB17, 0);
+	}
+	if (cs_mask & (1 << 1)) {
+		at91_set_B_periph(AT91_PIN_PD28, 0);
+	}
+	if (cs_mask & (1 << 2)) {
+		at91_set_A_periph(AT91_PIN_PD18, 0);
+	}
+	if (cs_mask & (1 << 3)) {
+		at91_set_A_periph(AT91_PIN_PD19, 0);
+	}
+	if (cs_mask & (1 << 4)) {
+		at91_set_gpio_output(AT91_PIN_PB17, 0);
+	}
+	if (cs_mask & (1 << 5)) {
+		at91_set_gpio_output(AT91_PIN_PD28, 0);
+	}
+	if (cs_mask & (1 << 6)) {
+		at91_set_gpio_output(AT91_PIN_PD18, 0);
+	}
+	if (cs_mask & (1 << 7)) {
+		at91_set_gpio_output(AT91_PIN_PD19, 0);
+	}
+
+}
+#endif
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ETXCK_EREFCK */
+	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERXDV */
+	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ERX0 */
+	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ERX1 */
+	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ERXER */
+	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ETXEN */
+	at91_set_A_periph(AT91_PIN_PA10, 0);	/* ETX0 */
+	at91_set_A_periph(AT91_PIN_PA11, 0);	/* ETX1 */
+	at91_set_A_periph(AT91_PIN_PA19, 0);	/* EMDIO */
+	at91_set_A_periph(AT91_PIN_PA18, 0);	/* EMDC */
+#ifndef CONFIG_RMII
+	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECRS */
+	at91_set_B_periph(AT91_PIN_PA30, 0);	/* ECOL */
+	at91_set_B_periph(AT91_PIN_PA8,  0);	/* ERX2 */
+	at91_set_B_periph(AT91_PIN_PA9,  0);	/* ERX3 */
+	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ERXCK */
+	at91_set_B_periph(AT91_PIN_PA6,  0);	/* ETX2 */
+	at91_set_B_periph(AT91_PIN_PA7,  0);	/* ETX3 */
+	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ETXER */
+#endif
+}
+#endif
diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c
index 9f03468..574f488 100644
--- a/cpu/arm926ejs/at91/clock.c
+++ b/cpu/arm926ejs/at91/clock.c
@@ -183,15 +183,23 @@ int at91_clock_init(unsigned long main_clock)
 	 * For now, assume this parentage won't change.
 	 */
 	mckr = at91_sys_read(AT91_PMC_MCKR);
+#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+	/* plla divisor by 2 */
+	plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
+#endif
 	freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS);
+
 	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));			/* prescale */
 #if defined(CONFIG_AT91RM9200)
 	mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
 #elif defined(CONFIG_AT91SAM9G20)
 	mck_rate_hz = (mckr & AT91_PMC_MDIV) ?
-		freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
+		freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;		/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
 	if (mckr & AT91_PMC_PDIV)
-		freq /= 2;		/* processor clock division */
+		freq /= 2;						/* processor clock division */
+#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
+	mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
+		freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
 #else
 	mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
 #endif