summaryrefslogtreecommitdiff
path: root/cpu/arm926ejs/at91
diff options
context:
space:
mode:
authorStelian Pop <stelian@popies.net>2008-11-09 00:14:46 +0100
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2008-11-21 01:41:14 +0100
commit3e0cda071a67cb5709e3fa4faf6b31a731859acc (patch)
treef41e0b3d1f5c09900d841c7737741698a91c79e3 /cpu/arm926ejs/at91
parentad229a44e162af0f65e57e4e3dc133d5f0364ecb (diff)
downloadu-boot-imx-3e0cda071a67cb5709e3fa4faf6b31a731859acc.zip
u-boot-imx-3e0cda071a67cb5709e3fa4faf6b31a731859acc.tar.gz
u-boot-imx-3e0cda071a67cb5709e3fa4faf6b31a731859acc.tar.bz2
AT91: Enable PLLB for USB
At least some (old ?) versions of the AT91Bootstrap do not set up the PLLB correctly to 48 MHz in order to make USB host function correctly. This patch sets up the PLLB to the same values Linux uses, and makes USB work ok on the following CPUs: - AT91CAP9 - AT91SAM9260 - AT91SAM9263 This patch also defines CONFIG_USB_STORAGE and CONFIG_CMD_FAT for all the relevant AT91CAP9/AT91SAM9 atmel boards. Signed-off-by: Stelian Pop <stelian@popies.net> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/arm926ejs/at91')
-rw-r--r--cpu/arm926ejs/at91/usb.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/cpu/arm926ejs/at91/usb.c b/cpu/arm926ejs/at91/usb.c
index 7cb082d..2f5c337 100644
--- a/cpu/arm926ejs/at91/usb.c
+++ b/cpu/arm926ejs/at91/usb.c
@@ -31,6 +31,15 @@
int usb_cpu_init(void)
{
+
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+ defined(CONFIG_AT91SAM9263)
+ /* Enable PLLB */
+ at91_sys_write(AT91_CKGR_PLLBR, CFG_AT91_PLLB);
+ while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB)
+ ;
+#endif
+
/* Enable USB host clock. */
at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_UHP);
#ifdef CONFIG_AT91SAM9261
@@ -51,6 +60,15 @@ int usb_cpu_stop(void)
#else
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_UHP);
#endif
+
+#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
+ defined(CONFIG_AT91SAM9263)
+ /* Disable PLLB */
+ at91_sys_write(AT91_CKGR_PLLBR, 0);
+ while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != 0)
+ ;
+#endif
+
return 0;
}