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| author | Sedji Gaouaou <sedji.gaouaou@atmel.com> | 2009-07-09 10:16:29 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2009-07-12 17:43:34 +0200 |
| commit | 22ee647380c42f44528f99b7c1b423725e542102 (patch) | |
| tree | 20e092ef880553d89245d23adc2b1f6b43200f89 /cpu/arm926ejs/at91/clock.c | |
| parent | c33c5990cec7ced9ef1ef148debbca34adafa12b (diff) | |
| download | u-boot-imx-22ee647380c42f44528f99b7c1b423725e542102.zip u-boot-imx-22ee647380c42f44528f99b7c1b423725e542102.tar.gz u-boot-imx-22ee647380c42f44528f99b7c1b423725e542102.tar.bz2 | |
at91: Introduction of at91sam9g45 SOC.
AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz.
It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of
peripherals.
The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES.
On the board you can find 2 USART, USB high speed,
a 480*272 LG lcd, ethernet, gpio/joystick/buttons.
Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
Diffstat (limited to 'cpu/arm926ejs/at91/clock.c')
| -rw-r--r-- | cpu/arm926ejs/at91/clock.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c index 9f03468..574f488 100644 --- a/cpu/arm926ejs/at91/clock.c +++ b/cpu/arm926ejs/at91/clock.c @@ -183,15 +183,23 @@ int at91_clock_init(unsigned long main_clock) * For now, assume this parentage won't change. */ mckr = at91_sys_read(AT91_PMC_MCKR); +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) + /* plla divisor by 2 */ + plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); +#endif freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS); + freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ #if defined(CONFIG_AT91RM9200) mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ #elif defined(CONFIG_AT91SAM9G20) mck_rate_hz = (mckr & AT91_PMC_MDIV) ? - freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ if (mckr & AT91_PMC_PDIV) - freq /= 2; /* processor clock division */ + freq /= 2; /* processor clock division */ +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) + mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ? + freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ #else mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ #endif |