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authorJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-04-05 13:06:31 +0200
committerJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>2009-04-05 13:06:31 +0200
commitb3acb6cd4059dfb29a5e99095d802717f53ff784 (patch)
tree0578103fde893d08e5b6127db4df18833ae3d075 /cpu/arm920t
parent677e62f43235de9a1701204d7bcea0fb3d233fa1 (diff)
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arm: clean cache management
unify arm cache management except for non standard cache as ARM7TDMI Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Diffstat (limited to 'cpu/arm920t')
-rw-r--r--cpu/arm920t/cpu.c73
1 files changed, 10 insertions, 63 deletions
diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index 83ee3f3..08c9339 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -38,13 +38,7 @@
DECLARE_GLOBAL_DATA_PTR;
#endif
-static void cp_delay (void)
-{
- volatile int i;
-
- /* copro seems to need some delay between reading and writing */
- for (i = 0; i < 100; i++);
-}
+static void cache_flush(void);
int cpu_init (void)
{
@@ -67,20 +61,15 @@ int cleanup_before_linux (void)
* we turn off caches etc ...
*/
- unsigned long i;
-
disable_interrupts ();
/* turn off I/D-cache */
- asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
- i &= ~(CR_C | CR_I);
- asm ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
-
+ icache_disable();
+ dcache_disable();
/* flush I/D-cache */
- i = 0;
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
+ cache_flush();
- return (0);
+ return 0;
}
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -88,55 +77,13 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
disable_interrupts ();
reset_cpu (0);
/*NOTREACHED*/
- return (0);
-}
-
-void icache_enable (void)
-{
- ulong reg;
-
- reg = get_cr (); /* get control reg. */
- cp_delay ();
- set_cr (reg | CR_I);
-}
-
-void icache_disable (void)
-{
- ulong reg;
-
- reg = get_cr ();
- cp_delay ();
- set_cr (reg & ~CR_I);
-}
-
-int icache_status (void)
-{
- return (get_cr () & CR_I) != 0;
-}
-
-#ifdef USE_920T_MMU
-/* It makes no sense to use the dcache if the MMU is not enabled */
-void dcache_enable (void)
-{
- ulong reg;
-
- reg = get_cr ();
- cp_delay ();
- set_cr (reg | CR_C);
+ return 0;
}
-void dcache_disable (void)
+/* flush I/D-cache */
+static void cache_flush (void)
{
- ulong reg;
-
- reg = get_cr ();
- cp_delay ();
- reg &= ~CR_C;
- set_cr (reg);
-}
+ unsigned long i = 0;
-int dcache_status (void)
-{
- return (get_cr () & CR_C) != 0;
+ asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
}
-#endif