Clean-up of cpu_arm920t and cpu_arm920t_s3c24x0 code

This patch re-formats the code in cpu/arm920t and cpu/arm920t/23c24x0 in
preparation for changes to add support for the Embest SBC2440-II Board.

The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
  non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports

It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009

Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no
new warnings or errors were found.

Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

1 files changed, 33 insertions, 30 deletions

diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 27f38b8..114427a 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -37,7 +37,7 @@
 
 
 .globl _start
-_start:	b       start_code
+_start:	b	start_code
 	ldr	pc, _undefined_instruction
 	ldr	pc, _software_interrupt
 	ldr	pc, _prefetch_abort
@@ -109,13 +109,13 @@ start_code:
 	/*
 	 * set the cpu to SVC32 mode
 	 */
-	mrs	r0,cpsr
-	bic	r0,r0,#0x1f
-	orr	r0,r0,#0xd3
-	msr	cpsr,r0
+	mrs	r0, cpsr
+	bic	r0, r0, #0x1f
+	orr	r0, r0, #0xd3
+	msr	cpsr, r0
 
-	bl coloured_LED_init
-	bl red_LED_on
+	bl	coloured_LED_init
+	bl	red_LED_on
 
 #if	defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
 	/*
@@ -135,19 +135,19 @@ copyex:
 	/* turn off the watchdog */
 
 # if defined(CONFIG_S3C2400)
-#  define pWTCON		0x15300000
-#  define INTMSK		0x14400008	/* Interupt-Controller base addresses */
+#  define pWTCON	0x15300000
+#  define INTMSK	0x14400008	/* Interupt-Controller base addresses */
 #  define CLKDIVN	0x14800014	/* clock divisor register */
 #else
-#  define pWTCON		0x53000000
-#  define INTMSK		0x4A000008	/* Interupt-Controller base addresses */
+#  define pWTCON	0x53000000
+#  define INTMSK	0x4A000008	/* Interupt-Controller base addresses */
 #  define INTSUBMSK	0x4A00001C
 #  define CLKDIVN	0x4C000014	/* clock divisor register */
 # endif
 
-	ldr     r0, =pWTCON
-	mov     r1, #0x0
-	str     r1, [r0]
+	ldr	r0, =pWTCON
+	mov	r1, #0x0
+	str	r1, [r0]
 
 	/*
 	 * mask all IRQs by setting all bits in the INTMR - default
@@ -180,8 +180,8 @@ copyex:
 relocate:				/* relocate U-Boot to RAM	    */
 	adr	r0, _start		/* r0 <- current position of code   */
 	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
-	cmp     r0, r1                  /* don't reloc during debug         */
-	beq     stack_setup
+	cmp	r0, r1			/* don't reloc during debug         */
+	beq	stack_setup
 
 	ldr	r2, _armboot_start
 	ldr	r3, _bss_start
@@ -198,8 +198,8 @@ copy_loop:
 	/* Set up the stack						    */
 stack_setup:
 	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
-	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area                      */
-	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                        */
+	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area              */
+	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo                 */
 #ifdef CONFIG_USE_IRQ
 	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
 #endif
@@ -297,8 +297,8 @@ cpu_init_crit:
 #define S_R1		4
 #define S_R0		0
 
-#define MODE_SVC 0x13
-#define I_BIT	 0x80
+#define MODE_SVC	0x13
+#define I_BIT		0x80
 
 /*
  * use bad_save_user_regs for abort/prefetch/undef/swi ...
@@ -311,7 +311,8 @@ cpu_init_crit:
 	ldr	r2, _armboot_start
 	sub	r2, r2, #(CONFIG_STACKSIZE)
 	sub	r2, r2, #(CONFIG_SYS_MALLOC_LEN)
-	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
+	/* set base 2 words into abort stack */
+	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
 	ldmia	r2, {r2 - r3}			@ get pc, cpsr
 	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC
 
@@ -324,12 +325,12 @@ cpu_init_crit:
 	.macro	irq_save_user_regs
 	sub	sp, sp, #S_FRAME_SIZE
 	stmia	sp, {r0 - r12}			@ Calling r0-r12
-	add     r7, sp, #S_PC
-	stmdb   r7, {sp, lr}^                   @ Calling SP, LR
-	str     lr, [r7, #0]                    @ Save calling PC
-	mrs     r6, spsr
-	str     r6, [r7, #4]                    @ Save CPSR
-	str     r0, [r7, #8]                    @ Save OLD_R0
+	add	r7, sp, #S_PC
+	stmdb	r7, {sp, lr}^			@ Calling SP, LR
+	str	lr, [r7, #0]			@ Save calling PC
+	mrs	r6, spsr
+	str	r6, [r7, #4]			@ Save CPSR
+	str	r0, [r7, #8]			@ Save OLD_R0
 	mov	r0, sp
 	.endm
 
@@ -338,18 +339,20 @@ cpu_init_crit:
 	mov	r0, r0
 	ldr	lr, [sp, #S_PC]			@ Get PC
 	add	sp, sp, #S_FRAME_SIZE
-	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
+	/* return & move spsr_svc into cpsr */
+	subs	pc, lr, #4
 	.endm
 
 	.macro get_bad_stack
 	ldr	r13, _armboot_start		@ setup our mode stack
 	sub	r13, r13, #(CONFIG_STACKSIZE)
 	sub	r13, r13, #(CONFIG_SYS_MALLOC_LEN)
-	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+	/* reserve a couple spots in abort stack */
+	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
 
 	str	lr, [r13]			@ save caller lr / spsr
 	mrs	lr, spsr
-	str     lr, [r13, #4]
+	str	lr, [r13, #4]
 
 	mov	r13, #MODE_SVC			@ prepare SVC-Mode
 	@ msr	spsr_c, r13