summaryrefslogtreecommitdiff
path: root/cpu/arm920t/start.S
diff options
context:
space:
mode:
authorwdenk <wdenk>2004-08-01 22:48:16 +0000
committerwdenk <wdenk>2004-08-01 22:48:16 +0000
commit281e00a3be453a169d854f824a460359d10f92bb (patch)
tree43dab398f1d6f601bb44df108427f7e0c611d68d /cpu/arm920t/start.S
parentcfca5e604d5692f081cc1a9185ca5dc6dc77599d (diff)
downloadu-boot-imx-281e00a3be453a169d854f824a460359d10f92bb.zip
u-boot-imx-281e00a3be453a169d854f824a460359d10f92bb.tar.gz
u-boot-imx-281e00a3be453a169d854f824a460359d10f92bb.tar.bz2
* Code cleanup
* Patch by Sascha Hauer, 28 Jun: - add generic support for Motorola i.MX architecture - add support for mx1ads, mx1fs2 and scb9328 boards * Patches by Marc Leeman, 23 Jul 2004: - Add define for the PCI/Memory Buffer Configuration Register - corrected comments in cpu/mpc824x/cpu_init.c * Add support for multiple serial interfaces (for example to allow modem dial-in / dial-out)
Diffstat (limited to 'cpu/arm920t/start.S')
-rw-r--r--cpu/arm920t/start.S24
1 files changed, 11 insertions, 13 deletions
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 0e372d0..78c470d 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -118,20 +118,17 @@ reset:
/* turn off the watchdog */
#if defined(CONFIG_S3C2400)
-#define pWTCON 0x15300000
-/* Interupt-Controller base addresses */
-#define INTMSK 0x14400008
-/* clock divisor register */
-#define CLKDIVN 0x14800014
+# define pWTCON 0x15300000
+# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define CLKDIVN 0x14800014 /* clock divisor register */
#elif defined(CONFIG_S3C2410)
-#define pWTCON 0x53000000
-/* Interupt-Controller base addresses */
-#define INTMSK 0x4A000008
-#define INTSUBMSK 0x4A00001C
-/* clock divisor register */
-#define CLKDIVN 0x4C000014
+# define pWTCON 0x53000000
+# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define INTSUBMSK 0x4A00001C
+# define CLKDIVN 0x4C000014 /* clock divisor register */
#endif
+#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
ldr r0, =pWTCON
mov r1, #0x0
str r1, [r0]
@@ -142,17 +139,18 @@ reset:
mov r1, #0xffffffff
ldr r0, =INTMSK
str r1, [r0]
-#if defined(CONFIG_S3C2410)
+# if defined(CONFIG_S3C2410)
ldr r1, =0x3ff
ldr r0, =INTSUBMSK
str r1, [r0]
-#endif
+# endif
/* FCLK:HCLK:PCLK = 1:2:4 */
/* default FCLK is 120 MHz ! */
ldr r0, =CLKDIVN
mov r1, #3
str r1, [r0]
+#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
/*
* we do sys-critical inits only at reboot,