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authorJens Scharsig <js_at_ng@scharsoft.de>2010-02-03 22:47:35 +0100
committerTom Rix <Tom.Rix@windriver.com>2010-02-12 12:31:55 -0600
commit98250e8e17fc76b3981708c6e63d41f875bf0359 (patch)
tree65125964ebf59637e493f173b64e06587d365eee /cpu/arm920t/at91/lowlevel_init.S
parent1b34f00c28a3023693d9b31e7bd1a9212af8352f (diff)
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prepare joining at91rm9200 into at91
* prepare joining at91 and at91rm9200 * add modified copy of soc files to cpu/arm920t/at91 to make possible to compile at91rm9200 boards in at91 tree instead of at91rm9200 * add header files with c structure defs for AT91 MC, ST and TC * the new cpu files are using at91 c structure soc access * please read README.soc-at91 for details Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
Diffstat (limited to 'cpu/arm920t/at91/lowlevel_init.S')
-rw-r--r--cpu/arm920t/at91/lowlevel_init.S164
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diff --git a/cpu/arm920t/at91/lowlevel_init.S b/cpu/arm920t/at91/lowlevel_init.S
new file mode 100644
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+++ b/cpu/arm920t/at91/lowlevel_init.S
@@ -0,0 +1,164 @@
+/*
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
+ * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
+ *
+ * Modified for the at91rm9200dk board by
+ * (C) Copyright 2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/at91_mc.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_pio.h>
+
+#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
+
+_MTEXT_BASE:
+#undef START_FROM_MEM
+#ifdef START_FROM_MEM
+ .word TEXT_BASE-PHYS_FLASH_1
+#else
+ .word TEXT_BASE
+#endif
+
+.globl lowlevel_init
+lowlevel_init:
+ ldr r1, =AT91_ASM_PMC_MOR
+ /* Main oscillator Enable register */
+#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
+ ldr r0, =0x0000FF01 /* Enable main oscillator */
+#else
+ ldr r0, =0x0000FF00 /* Disable main oscillator */
+#endif
+ str r0, [r1] /*AT91C_CKGR_MOR] */
+ /* Add loop to compensate Main Oscillator startup time */
+ ldr r0, =0x00000010
+LoopOsc:
+ subs r0, r0, #1
+ bhi LoopOsc
+
+ /* memory control configuration */
+ /* this isn't very elegant, but what the heck */
+ ldr r0, =SMRDATA
+ ldr r1, _MTEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #80
+pllloop:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne pllloop
+ /* delay - this is all done by guess */
+ ldr r0, =0x00010000
+ /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
+lock:
+ subs r0, r0, #1
+ bhi lock
+ ldr r0, =SMRDATA1
+ ldr r1, _MTEXT_BASE
+ sub r0, r0, r1
+ add r2, r0, #176
+sdinit:
+ /* the address */
+ ldr r1, [r0], #4
+ /* the value */
+ ldr r3, [r0], #4
+ str r3, [r1]
+ cmp r2, r0
+ bne sdinit
+
+ /* switch from FastBus to Asynchronous clock mode */
+ mrc p15, 0, r0, c1, c0, 0
+ orr r0, r0, #ARM920T_CONTROL
+ mcr p15, 0, r0, c1, c0, 0
+
+ /* everything is fine now */
+ mov pc, lr
+
+ .ltorg
+
+SMRDATA:
+ .word AT91_ASM_MC_EBI_CFG
+ .word CONFIG_SYS_EBI_CFGR_VAL
+ .word AT91_ASM_MC_SMC_CSR0
+ .word CONFIG_SYS_SMC_CSR0_VAL
+ .word AT91_ASM_PMC_PLLAR
+ .word CONFIG_SYS_PLLAR_VAL
+ .word AT91_ASM_PMC_PLLBR
+ .word CONFIG_SYS_PLLBR_VAL
+ .word AT91_ASM_PMC_MCKR
+ .word CONFIG_SYS_MCKR_VAL
+ /* here there's a delay */
+SMRDATA1:
+ .word AT91_ASM_PIOC_ASR
+ .word CONFIG_SYS_PIOC_ASR_VAL
+ .word AT91_ASM_PIOC_BSR
+ .word CONFIG_SYS_PIOC_BSR_VAL
+ .word AT91_ASM_PIOC_PDR
+ .word CONFIG_SYS_PIOC_PDR_VAL
+ .word AT91_ASM_MC_EBI_CSA
+ .word CONFIG_SYS_EBI_CSA_VAL
+ .word AT91_ASM_MC_SDRAMC_CR
+ .word CONFIG_SYS_SDRC_CR_VAL
+ .word AT91_ASM_MC_SDRAMC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91_ASM_MC_SDRAMC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL1
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91_ASM_MC_SDRAMC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL2
+ .word CONFIG_SYS_SDRAM1
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91_ASM_MC_SDRAMC_TR
+ .word CONFIG_SYS_SDRC_TR_VAL
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ .word AT91_ASM_MC_SDRAMC_MR
+ .word CONFIG_SYS_SDRC_MR_VAL3
+ .word CONFIG_SYS_SDRAM
+ .word CONFIG_SYS_SDRAM_VAL
+ /* SMRDATA1 is 176 bytes long */
+#endif /* CONFIG_SKIP_LOWLEVEL_INIT */