arm: update co-processor 15 access

import system.h from linux

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

1 files changed, 11 insertions, 47 deletions

diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c
index 1e94f7d..ef78bd9 100644
--- a/cpu/arm1176/cpu.c
+++ b/cpu/arm1176/cpu.c
@@ -34,34 +34,10 @@
 #include <common.h>
 #include <command.h>
 #include <s3c6400.h>
+#include <asm/system.h>
 
 static void cache_flush (void);
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1 (void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__(
-		"mrc	p15, 0, %0, c1, c0, 0   @ read control reg\n"
-		: "=r" (value)
-		:
-		: "memory");
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1 (unsigned long value)
-{
-	__asm__ __volatile__(
-		"mcr	p15, 0, %0, c1, c0, 0   @ write it back\n"
-		:
-		: "r" (value)
-		: "memory");
-
-	read_p15_c1();
-}
-
 static void cp_delay (void)
 {
 	volatile int i;
@@ -71,18 +47,6 @@ static void cp_delay (void)
 		__asm__ __volatile__("nop\n");
 }
 
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1 << 0)	/* mmu off/on */
-#define C1_ALIGN	(1 << 1)	/* alignment faults off/on */
-#define C1_DC		(1 << 2)	/* dcache off/on */
-#define C1_WB		(1 << 3)	/* merging write buffer on/off */
-#define C1_BIG_ENDIAN	(1 << 7)	/* big endian off/on */
-#define C1_SYS_PROT	(1 << 8)	/* system protection */
-#define C1_ROM_PROT	(1 << 9)	/* ROM protection */
-#define C1_IC		(1 << 12)	/* icache off/on */
-#define C1_HIGH_VECTORS	(1 << 13)	/* location of vectors: low/high */
-#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
-
 int cpu_init (void)
 {
 	return 0;
@@ -135,23 +99,23 @@ void icache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();	/* get control reg. */
+	reg = get_cr ();	/* get control reg. */
 	cp_delay ();
-	write_p15_c1 (reg | C1_IC);
+	set_cr (reg | CR_I);
 }
 
 void icache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_IC);
+	set_cr (reg & ~CR_I);
 }
 
 int icache_status (void)
 {
-	return (read_p15_c1 () & C1_IC) != 0;
+	return (get_cr () & CR_I) != 0;
 }
 
 /* It makes no sense to use the dcache if the MMU is not enabled */
@@ -159,23 +123,23 @@ void dcache_enable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg | C1_DC);
+	set_cr (reg | CR_C);
 }
 
 void dcache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_DC);
+	set_cr (reg & ~CR_C);
 }
 
 int dcache_status (void)
 {
-	return (read_p15_c1 () & C1_DC) != 0;
+	return (get_cr () & CR_C) != 0;
 }
 
 /* flush I/D-cache */