arm: Move cpu/$CPU to arch/arm/cpu/$CPU

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>

6 files changed, 0 insertions, 573 deletions

diff --git a/cpu/arm1176/s3c64xx/Makefile b/cpu/arm1176/s3c64xx/Makefile
deleted file mode 100644
index b527939..0000000
--- a/cpu/arm1176/s3c64xx/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2000-2003
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2008
-# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(SOC).a
-
-SOBJS	= reset.o
-
-COBJS-$(CONFIG_S3C6400)	+= cpu_init.o speed.o
-COBJS-y	+= timer.o
-
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
-
-all:	$(obj).depend $(START) $(LIB)
-
-$(LIB):	$(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/cpu/arm1176/s3c64xx/config.mk b/cpu/arm1176/s3c64xx/config.mk
deleted file mode 100644
index 14346cf..0000000
--- a/cpu/arm1176/s3c64xx/config.mk
+++ /dev/null
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-# Make ARMv5 to allow more compilers to work, even though its v6.
-PLATFORM_CPPFLAGS += -march=armv5t
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# =========================================================================
-PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
diff --git a/cpu/arm1176/s3c64xx/cpu_init.S b/cpu/arm1176/s3c64xx/cpu_init.S
deleted file mode 100644
index df88cba..0000000
--- a/cpu/arm1176/s3c64xx/cpu_init.S
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
- *
- * Copyright (C) 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/arch/s3c6400.h>
-
-	.globl mem_ctrl_asm_init
-mem_ctrl_asm_init:
-	/* DMC1 base address 0x7e001000 */
-	ldr	r0, =ELFIN_DMC1_BASE
-
-	ldr	r1, =0x4
-	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
-
-	ldr	r1, =DMC_DDR_REFRESH_PRD
-	str	r1, [r0, #INDEX_DMC_REFRESH_PRD]
-
-	ldr	r1, =DMC_DDR_CAS_LATENCY
-	str	r1, [r0, #INDEX_DMC_CAS_LATENCY]
-
-	ldr	r1, =DMC_DDR_t_DQSS
-	str	r1, [r0, #INDEX_DMC_T_DQSS]
-
-	ldr	r1, =DMC_DDR_t_MRD
-	str	r1, [r0, #INDEX_DMC_T_MRD]
-
-	ldr	r1, =DMC_DDR_t_RAS
-	str	r1, [r0, #INDEX_DMC_T_RAS]
-
-	ldr	r1, =DMC_DDR_t_RC
-	str	r1, [r0, #INDEX_DMC_T_RC]
-
-	ldr	r1, =DMC_DDR_t_RCD
-	ldr	r2, =DMC_DDR_schedule_RCD
-	orr	r1, r1, r2
-	str	r1, [r0, #INDEX_DMC_T_RCD]
-
-	ldr	r1, =DMC_DDR_t_RFC
-	ldr	r2, =DMC_DDR_schedule_RFC
-	orr	r1, r1, r2
-	str	r1, [r0, #INDEX_DMC_T_RFC]
-
-	ldr	r1, =DMC_DDR_t_RP
-	ldr	r2, =DMC_DDR_schedule_RP
-	orr	r1, r1, r2
-	str	r1, [r0, #INDEX_DMC_T_RP]
-
-	ldr	r1, =DMC_DDR_t_RRD
-	str	r1, [r0, #INDEX_DMC_T_RRD]
-
-	ldr	r1, =DMC_DDR_t_WR
-	str	r1, [r0, #INDEX_DMC_T_WR]
-
-	ldr	r1, =DMC_DDR_t_WTR
-	str	r1, [r0, #INDEX_DMC_T_WTR]
-
-	ldr	r1, =DMC_DDR_t_XP
-	str	r1, [r0, #INDEX_DMC_T_XP]
-
-	ldr	r1, =DMC_DDR_t_XSR
-	str	r1, [r0, #INDEX_DMC_T_XSR]
-
-	ldr	r1, =DMC_DDR_t_ESR
-	str	r1, [r0, #INDEX_DMC_T_ESR]
-
-	ldr	r1, =DMC1_MEM_CFG
-	str	r1, [r0, #INDEX_DMC_MEMORY_CFG]
-
-	ldr	r1, =DMC1_MEM_CFG2
-	str	r1, [r0, #INDEX_DMC_MEMORY_CFG2]
-
-	ldr	r1, =DMC1_CHIP0_CFG
-	str	r1, [r0, #INDEX_DMC_CHIP_0_CFG]
-
-	ldr	r1, =DMC_DDR_32_CFG
-	str	r1, [r0, #INDEX_DMC_USER_CONFIG]
-
-	/* DMC0 DDR Chip 0 configuration direct command reg */
-	ldr	r1, =DMC_NOP0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* Precharge All */
-	ldr	r1, =DMC_PA0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* Auto Refresh 2 time */
-	ldr	r1, =DMC_AR0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* MRS */
-	ldr	r1, =DMC_mDDR_EMR0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* Mode Reg */
-	ldr	r1, =DMC_mDDR_MR0
-	str	r1, [r0, #INDEX_DMC_DIRECT_CMD]
-
-	/* Enable DMC1 */
-	mov	r1, #0x0
-	str	r1, [r0, #INDEX_DMC_MEMC_CMD]
-
-check_dmc1_ready:
-	ldr	r1, [r0, #INDEX_DMC_MEMC_STATUS]
-	mov	r2, #0x3
-	and	r1, r1, r2
-	cmp	r1, #0x1
-	bne	check_dmc1_ready
-	nop
-
-	mov	pc, lr
-
-	.ltorg
diff --git a/cpu/arm1176/s3c64xx/reset.S b/cpu/arm1176/s3c64xx/reset.S
deleted file mode 100644
index eae572e..0000000
--- a/cpu/arm1176/s3c64xx/reset.S
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2009 Samsung Electronics.
- * Minkyu Kang <mk7.kang@samsung.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm/arch/s3c6400.h>
-
-.globl reset_cpu
-reset_cpu:
-	ldr	r1, =ELFIN_CLOCK_POWER_BASE
-	ldr	r2, [r1, #SYS_ID_OFFSET]
-	ldr	r3, =0xffff
-	and	r2, r3, r2, lsr #12
-	str	r2, [r1, #SW_RST_OFFSET]
-_loop_forever:
-	b	_loop_forever
diff --git a/cpu/arm1176/s3c64xx/speed.c b/cpu/arm1176/s3c64xx/speed.c
deleted file mode 100644
index 11962ac..0000000
--- a/cpu/arm1176/s3c64xx/speed.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This code should work for both the S3C2400 and the S3C2410
- * as they seem to have the same PLL and clock machinery inside.
- * The different address mapping is handled by the s3c24xx.h files below.
- */
-
-#include <common.h>
-#include <asm/arch/s3c6400.h>
-
-#define APLL 0
-#define MPLL 1
-#define EPLL 2
-
-/* ------------------------------------------------------------------------- */
-/*
- * NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-static ulong get_PLLCLK(int pllreg)
-{
-	ulong r, m, p, s;
-
-	switch (pllreg) {
-	case APLL:
-		r = APLL_CON_REG;
-		break;
-	case MPLL:
-		r = MPLL_CON_REG;
-		break;
-	case EPLL:
-		r = EPLL_CON0_REG;
-		break;
-	default:
-		hang();
-	}
-
-	m = (r >> 16) & 0x3ff;
-	p = (r >> 8) & 0x3f;
-	s = r & 0x7;
-
-	return m * (CONFIG_SYS_CLK_FREQ / (p * (1 << s)));
-}
-
-/* return ARMCORE frequency */
-ulong get_ARMCLK(void)
-{
-	ulong div;
-
-	div = CLK_DIV0_REG;
-
-	return get_PLLCLK(APLL) / ((div & 0x7) + 1);
-}
-
-/* return FCLK frequency */
-ulong get_FCLK(void)
-{
-	return get_PLLCLK(APLL);
-}
-
-/* return HCLK frequency */
-ulong get_HCLK(void)
-{
-	ulong fclk;
-
-	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
-	uint hclk_div = ((CLK_DIV0_REG >> 8) & 0x1) + 1;
-
-	/*
-	 * Bit 7 exists on s3c6410, and not on s3c6400, it is reserved on
-	 * s3c6400 and is always 0, and it is indeed running in ASYNC mode
-	 */
-	if (OTHERS_REG & 0x80)
-		fclk = get_FCLK();		/* SYNC Mode	*/
-	else
-		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
-
-	return fclk / (hclk_div * hclkx2_div);
-}
-
-/* return PCLK frequency */
-ulong get_PCLK(void)
-{
-	ulong fclk;
-	uint hclkx2_div = ((CLK_DIV0_REG >> 9) & 0x7) + 1;
-	uint pre_div = ((CLK_DIV0_REG >> 12) & 0xf) + 1;
-
-	if (OTHERS_REG & 0x80)
-		fclk = get_FCLK();		/* SYNC Mode	*/
-	else
-		fclk = get_PLLCLK(MPLL);	/* ASYNC Mode	*/
-
-	return fclk / (hclkx2_div * pre_div);
-}
-
-/* return UCLK frequency */
-ulong get_UCLK(void)
-{
-	return get_PLLCLK(EPLL);
-}
-
-int print_cpuinfo(void)
-{
-	printf("\nCPU:     S3C6400@%luMHz\n", get_ARMCLK() / 1000000);
-	printf("         Fclk = %luMHz, Hclk = %luMHz, Pclk = %luMHz ",
-	       get_FCLK() / 1000000, get_HCLK() / 1000000,
-	       get_PCLK() / 1000000);
-
-	if (OTHERS_REG & 0x80)
-		printf("(SYNC Mode) \n");
-	else
-		printf("(ASYNC Mode) \n");
-	return 0;
-}
diff --git a/cpu/arm1176/s3c64xx/timer.c b/cpu/arm1176/s3c64xx/timer.c
deleted file mode 100644
index 9768319..0000000
--- a/cpu/arm1176/s3c64xx/timer.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/proc-armv/ptrace.h>
-#include <asm/arch/s3c6400.h>
-#include <div64.h>
-
-static ulong timer_load_val;
-
-#define PRESCALER	167
-
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
-	return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
-
-/* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
-{
-	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-	return timers->TCNTO4;
-}
-
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
-int timer_init(void)
-{
-	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-	/* use PWM Timer 4 because it has no output */
-	/*
-	 * We use the following scheme for the timer:
-	 * Prescaler is hard fixed at 167, divider at 1/4.
-	 * This gives at PCLK frequency 66MHz approx. 10us ticks
-	 * The timer is set to wrap after 100s, at 66MHz this obviously
-	 * happens after 10,000,000 ticks. A long variable can thus
-	 * keep values up to 40,000s, i.e., 11 hours. This should be
-	 * enough for most uses:-) Possible optimizations: select a
-	 * binary-friendly frequency, e.g., 1ms / 128. Also calculate
-	 * the prescaler automatically for other PCLK frequencies.
-	 */
-	timers->TCFG0 = PRESCALER << 8;
-	if (timer_load_val == 0) {
-		timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
-		timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
-	}
-
-	/* load value for 10 ms timeout */
-	lastdec = timers->TCNTB4 = timer_load_val;
-	/* auto load, manual update of Timer 4 */
-	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
-		TCON_4_UPDATE;
-
-	/* auto load, start Timer 4 */
-	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
-	timestamp = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	ulong now = read_timer();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + timer_load_val - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	/* We overrun in 100s */
-	return (ulong)(timer_load_val / 100);
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = read_timer();
-	timestamp = 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer_masked(void)
-{
-	unsigned long long res = get_ticks();
-	do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
-	return res;
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = (usec + 9) / 10;
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)/* loop till event */
-		 /*NOP*/;
-}