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| author | Terry Lv <r65388@freescale.com> | 2009-10-29 19:19:00 +0800 |
|---|---|---|
| committer | Terry Lv <r65388@freescale.com> | 2009-11-03 18:22:03 +0800 |
| commit | ba816f983f5dac44d9f4461906b9bc0101237ac8 (patch) | |
| tree | 52d3b83aa1cc146b88933f75b0a65c2dc813ea28 /cpu/arm1136/start.S | |
| parent | 3227c278048e6b13397d9d0793e77e703649d7de (diff) | |
| download | u-boot-imx-ba816f983f5dac44d9f4461906b9bc0101237ac8.zip u-boot-imx-ba816f983f5dac44d9f4461906b9bc0101237ac8.tar.gz u-boot-imx-ba816f983f5dac44d9f4461906b9bc0101237ac8.tar.bz2 | |
u-boot v2009.08 sd/mmc support.
Signed-off-by: Terry Lv <r65388@freescale.com>
Diffstat (limited to 'cpu/arm1136/start.S')
| -rw-r--r-- | cpu/arm1136/start.S | 42 |
1 files changed, 2 insertions, 40 deletions
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 57f13ef..b1d7087 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -130,6 +130,7 @@ next: #endif b setup_env +#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* ************************************************************************* * @@ -166,7 +167,7 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ - +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ .section ".text.setup", "ax" @@ -263,45 +264,6 @@ _start_armboot: .word start_armboot #endif /* CONFIG_ONENAND_IPL */ #endif /* CONFIG_NAND_SPL */ -/* - ************************************************************************* - * - * CPU_init_critical registers - * - * setup important registers - * setup memory timing - * - ************************************************************************* - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -cpu_init_crit: - /* - * flush v4 I/D caches - */ - mov r0, #0 - mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ - mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ - - /* - * disable MMU stuff and caches - */ - mrc p15, 0, r0, c1, c0, 0 - bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) - bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) - orr r0, r0, #0x00000002 @ set bit 2 (A) Align - orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache - mcr p15, 0, r0, c1, c0, 0 - - /* - * Jump to board specific initialization... The Mask ROM will have already initialized - * basic memory. Go here to bump up clock rate and handle wake up conditions. - */ - mov ip, lr /* persevere link reg across call */ - bl lowlevel_init /* go setup pll,mux,memory */ - mov lr, ip /* restore link */ - mov pc, lr /* back to my caller */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - #ifndef CONFIG_PRELOADER /* ************************************************************************* |