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| author | Fred Fan <r01011@freescale.com> | 2009-02-23 13:34:09 +0800 |
|---|---|---|
| committer | Fred Fan <r01011@freescale.com> | 2009-09-09 17:15:27 +0800 |
| commit | d409f3fd05bef817c37bade4b6a803da80dc7ad0 (patch) | |
| tree | d7651f6c09179ff7e72d904dd1b047645840a09b /cpu/arm1136/start.S | |
| parent | 6259800e38b3da575a8436d5616b3920c77f25f5 (diff) | |
| download | u-boot-imx-d409f3fd05bef817c37bade4b6a803da80dc7ad0.zip u-boot-imx-d409f3fd05bef817c37bade4b6a803da80dc7ad0.tar.gz u-boot-imx-d409f3fd05bef817c37bade4b6a803da80dc7ad0.tar.bz2 | |
ENGR00094619 Support i.MX31 3stack board
Support boot from NAND Flash
Add driver for i.MX31 NFC
Upgate U-Boot to support NAND boot
Signed-off-by: Xinyu Chen <xinyu.chen@freescale.com>
Diffstat (limited to 'cpu/arm1136/start.S')
| -rw-r--r-- | cpu/arm1136/start.S | 113 |
1 files changed, 84 insertions, 29 deletions
diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 957f438..a957ccc 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -85,40 +85,15 @@ _end_vect: ************************************************************************* */ -_TEXT_BASE: - .word TEXT_BASE - -.globl _armboot_start -_armboot_start: - .word _start - /* - * These are defined in the board-specific linker script. + * the actual reset code */ -.globl _bss_start -_bss_start: - .word __bss_start - -.globl _bss_end -_bss_end: - .word _end -#ifdef CONFIG_USE_IRQ -/* IRQ stack memory (calculated at run-time) */ -.globl IRQ_STACK_START -IRQ_STACK_START: - .word 0x0badc0de - -/* IRQ stack memory (calculated at run-time) */ -.globl FIQ_STACK_START -FIQ_STACK_START: - .word 0x0badc0de +#ifdef CONFIG_NAND_BOOT +.section ".text.head", "x" #endif -/* - * the actual reset code - */ - +.globl reset reset: /* * set the cpu to SVC32 mode @@ -150,6 +125,86 @@ next: #ifndef CONFIG_SKIP_LOWLEVEL_INIT bl cpu_init_crit #endif + b setup_env + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ +cpu_init_crit: + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + mcr p15, 0, r0, c1, c0, 0 + + /* + * Jump to board specific initialization... The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle wake up conditions. + */ + mov ip, lr /* persevere link reg across call */ + bl lowlevel_init /* go setup pll,mux,memory */ + mov lr, ip /* restore link */ + mov pc, lr /* back to my caller */ + + +#ifdef CONFIG_NAND_BOOT +.section ".text.setup" +#endif + +.globl _TEST_BASE +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: +#ifndef CONFIG_NAND_BOOT + .word _start +#else + .word reset +#endif + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +setup_env: #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ |