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| author | Wheatley Travis <Travis.Wheatley@freescale.com> | 2008-05-02 13:35:15 -0700 |
|---|---|---|
| committer | Wolfgang Denk <wd@denx.de> | 2008-05-09 20:46:48 +0200 |
| commit | f5a24259190c388c2527bdc49fee34577d862cc7 (patch) | |
| tree | e77d0df2fc72dfd1a26c993785dae2250738eb2d /cpu/74xx_7xx | |
| parent | 4d31cdc45d3592a5545a649fb5a24b458a4e4b72 (diff) | |
| download | u-boot-imx-f5a24259190c388c2527bdc49fee34577d862cc7.zip u-boot-imx-f5a24259190c388c2527bdc49fee34577d862cc7.tar.gz u-boot-imx-f5a24259190c388c2527bdc49fee34577d862cc7.tar.bz2 | |
7450 and 86xx L2 cache invalidate bug corrections
The 7610 and related parts have an L2IP bit in the L2CR that is
monitored to signal when the L2 cache invalidate is complete whereas the
7450 and related parts utilize L2I for this purpose. However, the
current code does not account for this difference. Additionally the 86xx
L2 cache invalidate code used an "andi" instruction where an "andis"
instruction should have been used.
This patch addresses both of these bugs.
Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
Acked-By: Jon Loeliger <jdl@freescale.com>
Diffstat (limited to 'cpu/74xx_7xx')
| -rw-r--r-- | cpu/74xx_7xx/cache.S | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S index a793d79..3a745cb 100644 --- a/cpu/74xx_7xx/cache.S +++ b/cpu/74xx_7xx/cache.S @@ -329,14 +329,28 @@ _GLOBAL(dcache_status) blr /* - * Invalidate L2 cache using L2I and polling L2IP + * Invalidate L2 cache using L2I and polling L2IP or L2I */ _GLOBAL(l2cache_invalidate) sync + mfspr r3, l2cr oris r3, r3, L2CR_L2I@h sync mtspr l2cr, r3 sync + mfspr r3, PVR + sync + rlwinm r3, r3, 16,16,31 + cmpli 0,r3,0x8000 /* 7451, 7441 */ + beq 0,inv_7450 + cmpli 0,r3,0x8001 /* 7455, 7445 */ + beq 0,inv_7450 + cmpli 0,r3,0x8002 /* 7457, 7447 */ + beq 0,inv_7450 + cmpli 0,r3,0x8003 /* 7447A */ + beq 0,inv_7450 + cmpli 0,r3,0x8004 /* 7448 */ + beq 0,inv_7450 invl2: mfspr r3, l2cr andi. r3, r3, L2CR_L2IP @@ -348,6 +362,11 @@ invl2: mtspr l2cr, r3 sync blr +inv_7450: + mfspr r3, l2cr + andis. r3, r3, L2CR_L2I@h + bne inv_7450 + blr /* * Enable L2 cache |