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author | Bin Meng <bmeng.cn@gmail.com> | 2015-04-24 18:10:05 +0800 |
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committer | Simon Glass <sjg@chromium.org> | 2015-04-29 18:51:49 -0600 |
commit | b5b6b0196017da0c2b4d483a2cd59be7810c1d7a (patch) | |
tree | 99b3f12b2f5f5f207fbec089a184562847cc990e /configs/spear310_nand_defconfig | |
parent | 5e2400e8f873a1b7ee840554e4157c5f7900a863 (diff) | |
download | u-boot-imx-b5b6b0196017da0c2b4d483a2cd59be7810c1d7a.zip u-boot-imx-b5b6b0196017da0c2b4d483a2cd59be7810c1d7a.tar.gz u-boot-imx-b5b6b0196017da0c2b4d483a2cd59be7810c1d7a.tar.bz2 |
x86: Support platform PIRQ routing
On x86 boards, platform chipset receives up to four different
interrupt signals from PCI devices (INTA/B/C/D), which in turn
will be routed to chipset internal PIRQ lines then routed to
8259 PIC finally if configuring the whole system to work under
the so-called PIC mode (in contrast to symmetric IO mode which
uses IOAPIC).
We add two major APIs to aid this, one for routing PIRQ and the
other one for generating a PIRQ routing table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'configs/spear310_nand_defconfig')
0 files changed, 0 insertions, 0 deletions